Abstract: A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

Abstract: A linear amplifier outputs differential signals corresponding to differential signals input to a first signal input terminal and a second signal input terminal, and includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third transistor, a fourth transistor, a differential amplifier, and a signal processing circuit. The signal processing circuit includes a first transistor and a second transistor, and includes a resistor as a common voltage output part that outputs a common voltage. The differential amplifier receives the common voltage and a reference voltage, and applies a voltage corresponding to the voltage difference between the common voltage and the reference voltage to the control terminals of the transistors.

Abstract: Provided is a voltage-controlled oscillator capable of suppressing performance deterioration due to a leak current of a variable capacitive element. Each of the first capacitive circuit and the second capacitive circuit includes a variable capacitive element, a capacitive element, a detection circuit, and a compensation circuit. The variable capacitive element is provided between nodes. A capacitance value of variable capacitive element depends on a voltage value between the nodes. The detection circuit applies a bias voltage value to the second node, and detects an amount of leak current flowing through the variable capacitive element. The compensation circuit causes a current for compensating for the leak current of the variable capacitive element to flow through the first node on the basis of a detection result of the detection circuit.

Abstract: The video signal transmission and reception system performs transmission of a video signal and a control signal between the video signal transmitting device and the video signal receiving device via a common transmission line. The video signal transmitting device includes a video signal transmitter, a control signal transmitter and receiver, a filter circuit, a controller, and a camera. The video signal receiving device includes a video signal receiver, a control signal transmitter and receiver, a filter circuit, and a controller. By performing time management control performed by the controller or the controller such that the period of the transient state of transmission of the video signal is within the non-communication period of the control signal, interference between the video signal and the control signal in the period of the transient state of transmission of the video signal is suppressed.

Abstract: An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.

Abstract: A transmission/reception system 1 includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P111 and P112 that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P111 and P112 is constant over a state where no electric power is supplied and an idle state.

Abstract: A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Bm outputs an m-th input signal when the signal levels of both an m-th control signal Cm and an n-th control signal Cn of M control signals are significant, and the m-th pre-stage buffer Bm enters into a high-impedance state when the signal level of at least one of the m-th control signal Cm and the n-th control signal Cn is non-significant. The output buffer Bout sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.

Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.

Abstract: A PLL frequency synthesizer includes a voltage controlled oscillator that outputs an oscillation signal having a frequency corresponding to a control voltage value, a phase comparison unit that outputs a phase difference signal representing a phase difference between a feedback oscillation signal and a reference oscillation signal, a charge pump that outputs a charge and discharge current according to the phase difference, a loop filter that outputs the control voltage value, which is increased or decreased according to a charge and discharge amount of a capacitive element, to the voltage controlled oscillator, a detection unit that detects a change rate of the control voltage value, and a control unit that adjusts the charge and discharge current, a characteristic of the loop filter, or a characteristic of the voltage controlled oscillator based on a detection result of the detection unit.

Abstract: A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Bm outputs an m-th input signal when the signal levels of both an m-th control signal Cm and an n-th control signal Cn of M control signals are significant, and the m-th pre-stage buffer Bm enters into a high-impedance state when the signal level of at least one of the m-th control signal Cm and the n-th control signal Cn is non-significant. The output buffer Bout sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.

Abstract: This embodiment relates to a transmitter and the like that prevent an increase of the number of cables of an external interface even when the types of signals to be transmitted increase. The transmitter includes a latch circuit, an encoder, a serializer, and a selector. The latch circuit keeps a level of each of a plurality of signals at the timing specified by a sampling clock, and then, outputs the plurality of signals as a parallel data signal. The encoder generates an encoded parallel data signal based on the parallel data signal from the latch circuit. The serializer generates a serial data signal based on the encoded parallel data signal from the encoder. The sampling clock has a frequency higher than a transmission rate of the fastest signal of the plurality of signals.

Abstract: This embodiment relates to a transmitter that has a structure to suppress an increase in device occupancy area on a semiconductor substrate. The transmitter includes an output driver, a duplication driver, a reference voltage generation unit, a first selection unit, a second selection unit, a comparison unit, and a control unit. The first selection unit selects a first or second test voltage outputted from a duplication driver in which a resistance value is set in cooperation with the output driver. The second selection unit selects a first or second reference voltage outputted from the reference voltage generation unit. The comparison unit compares magnitudes of the first test voltage and the first reference voltage during a first operation period and compares magnitudes of the second test voltage and the second reference voltage during a second operation period different from the first operation period.

Abstract: An equalizer adjusting device includes a comparator, an inequality counter, an adjuster, and the like. The comparator performs magnitude comparison between a voltage value Vout of each bit output from an equalizer and a threshold value MonLVL and outputs a logical value MonSMP according to a result of the comparison. The inequality counter inputs a logical value DatSMP output from a sampler in accordance with the result of magnitude comparison between the voltage value Vout of each bit and a reference value, and the logical value MonSMP output from the comparator and counts events in which the logical value DatSMP and the logical value MonSMP differ from each other, every period. The adjuster adjusts a gain of the equalizer and the threshold value MonLVL of the comparator based on a counted value of the inequality counter.

Abstract: The present invention relates to a video signal transmission device and the like that can support a variety of system specifications. The device includes a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals having a packet configuration of size corresponding to the number of pixels and the number of tone bits of a color signal constituting a video signal. At this time, a control signal including a pulse having a width corresponding to the number of pixels and the number of tone bits is also generated. The encoder unit applies encoding processing having encoding efficiencies that are different between a first period and a second period of a control signal that are distinguished depending on existence or non-existence of a pulse to the block signals.

Abstract: A PLL circuit of one embodiment has a structure for preferably setting the FV characteristic of an LC-VCO. The PLL circuit includes a voltage controlled oscillator, a phase comparator, a charge pump, a loop filter, and an FV characteristic adjustment unit setting the FV characteristic. The voltage controlled oscillator has an FV characteristic indicating the relationship between a control signal and a frequency and outputs an oscillation signal having a frequency corresponding to the control signal based on the FV characteristic. The phase comparator detects a phase difference between an input signal and the control signal. The charge pump outputs a corrected voltage value changed according to the phase difference. The loop filter outputs a control voltage value changed in response to corrected voltage value variations. The FV characteristic adjustment unit generates an FV characteristic control signal by a mean corrected voltage value.

Abstract: One embodiment relates to a transmitting device, a receiving device, and the like for preventing increases in the number of communication links, power consumption, and circuit layout area. The transmitting device includes a high-speed signal generator, a low-speed signal generator, and a signal superimposing unit. The high-speed signal generator generates a high-speed signal having a limited frequency band. The low-speed signal generator generates a low-speed signal having a frequency lower than the frequency band of the high-speed signal. The signal superimposing unit outputs a superimposed signal of the high-speed signal and the low-speed signal. The receiving device includes a signal separator and a recovery unit. The signal separator separates the received signal into the high-speed signal and the low-speed signal. The recovery unit performs frequency tracking based on the separated low-speed signal and performs phase tracking based on the separated high-speed signal.

Abstract: A PLL circuit includes a phase comparator, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider, and a phase compensator 70. The loop filter 30 includes a resistor 31, a first capacitance element 32, and a second capacitance element 33. The phase compensator 70 is provided in parallel to the charge pump 20 and adds a differentiation term to an open-loop transfer function. The phase compensator 70 includes a buffer 71 receiving a phase difference signal output from the phase comparator and a third capacitance element 72 provided between an output terminal of the buffer 71 and an input terminal of the loop filter 30.

Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: The signal multiplexer 1 inputs two selection signals CLK<1>, CLK<2> that sequentially reach significant levels, inputs two input signals IN<1>, IN<2>, and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN<m> of the two input signals when an m-th selection signal CLK<m> of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.

Abstract: Provided is a voltage-controlled oscillator capable of suppressing performance deterioration due to a leak current of a variable capacitive element. Each of the first capacitive circuit and the second capacitive circuit includes a variable capacitive element, a capacitive element, a detection circuit, and a compensation circuit. The variable capacitive element is provided between nodes. A capacitance value of variable capacitive element depends on a voltage value between the nodes. The detection circuit applies a bias voltage value to the second node, and detects an amount of leak current flowing through the variable capacitive element. The compensation circuit causes a current for compensating for the leak current of the variable capacitive element to flow through the first node on the basis of a detection result of the detection circuit.