Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A computer object processing system for, during selected iterations, generating an object, such as an expression defining an image. During an initial iteration, a predetermined number of seed objects are generated, each seed object defining an object for the initial iteration. During each successive iteration, a predetermined number of mutated objects are generated (i) in response to an operator selected one of the seed objects during the initial iteration and (ii) in response to a an operator selected object during each iteration after the initial iteration. During each iteration one of the seed objects or one of the mutated objects is selected for use in generating a mutated object during a subsequent iteration.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.

Abstract: A resistor circuit includes a resistance control circuit and at least one insulated gate field effect transistor. The resistance control circuit includes a control signal output element including a reference transistor for generating a resistance control signal in response to an internal control signal to maintain the reference transistor at a selected resistance value and a resistance value control element including a reference resistor for generating a circuit control signal for controlling the resistance value of the reference transistor in relation to the resistance value provided by the reference resistor. The field effect transistor is controlled by the resistance control signal to provide a resistance value which is a function of the resistance value of the reference transistor (and therefore of the reference resistor) and ratios of selected physical characteristics of the reference transistor.

Abstract: A partition establishment arrangement for use in a computer system comprising a plurality of processors interconnected by a communications network. The communications network comprises a plurality of communications nodes connected in a series of levels, with the nodes of at least some of the levels being controllable to connect to multiple ones of the nodes in a subsequent level. The partition establishment arrangement determines the controlling of the communication nodes to facilitate the partitioning of the processors into a plurality of partitions. The partition establishment arrangement, in a plurality of iterations, identifies conflict sets of processors to be assigned to respective partitions at a level, each conflict set identifying partitions for which, at a selected level, a processor may be connected to the same communications nodes in the next level.

Abstract: A compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer. The compiler comprises a front end which generates a parse tree from a source code. In generating the parse tree, the front end coordinates the compilation of type conversion operations and promotion operations such that run-time efficiency is maximized. In other words, the front end compiles the type conversion operations and promotion operations in an order which maximizes run-time efficiency.

Abstract: A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.

Abstract: A monolithic processing chip for a parallel processing system comprises a processor circuit and a memory circuit. The processor circuit processes data received from said associated memory circuit in accordance with processor control signals to generate processed data. The memory circuit includes a plurality of registers for storing data, each register including at least one data storage cell including at least one dynamic memory data bit store for storing a data bit. The memory circuit is responsive to memory control signals and register address signals to transmit stored data from the registers to the processor for processing and to store processed data received from the processor circuit in the register identified by the register address signals.

Abstract: A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network.

Abstract: An optimizer for optimizing an intermediate representation (IR) tree having multiple nodes. The IR tree represents a partial compilation of a source code. The source code is written using a high level language supporting data parallel processing. According to the present invention, the optimizer optimizes the IR tree by minimizing the number and size of temporary parallel variables in the IR tree. Such minimization optimizes the IR tree because temporary parallel variables require an enormous amount of space in memory.

Abstract: A system processes directed graphs, each directed graph comprising a plurality of nodes interconnected by arrows defining a relationship among the nodes, each node defining a selected attribute. The system comprises an initial population means, a subsequent generation population generating means, and a competition simulation means. The initial population means provides an initial population of directed graphs that comprises an initial current generation during an initial iteration. The subsequent generation population generating means generates, in response to selected ones of the directed graphs in each of a plurality of current generations, modified directed graphs for use generation during a subsequent iteration.

Abstract: Apparatus is described for allocating the resources of a parallel computer. The computer is divided into a plurality of processor arrays, a plurality of host computers are provided, and the host computers and the arrays are interfaced by an interconnection means that can connect any host computer to any one or more of the arrays. A specific connection means comprises a plurality of first multiplexers, one for each array, for writing data from any host computer to any array; a plurality of second multiplexers, one for each host computer, for reading from any array to any host computer; and control means for controlling the multiplexers so as to connect the host computers and arrays as desired by the users. The control means comprises a status register which specifies the connections between the host computers and the processor arrays as specified by the users.

Abstract: A massively parallel computer system including a plurality of processing nodes under control of a system controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises at least one processor, a memory, and a router node connected to the communications links for transferring in a series of message transfer cycles messages over the communications links. The controller enables each processing node to establish a message queue in its memory. The controller further enables storage of messages received by the processing nodes for their respective processors during a message transfer cycle to be stored in the message queue.

Abstract: A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion.

Abstract: A method and apparatus are described for improving the utilization of a parallel computer by allocating the resources of the parallel computer among a large number of users. A parallel computer is subdivided among a large number of users to meet the requirements of a multiplicity of databases and programs that are run simultaneously on the computer. This is accomplished by device(s) for dividing the parallel computer into a plurality of processor arrays, each of which can be used independently of the others. This division is made dynamically in the sense that the division can readily be altered and indeed in a time sharing environment may be altered between two successive time slots of the frame. Further, the parallel computer is organized so as to permit the simulation of additional parallel processors by each physical processor in the array and to provide for communication among the simulated parallel processors. Device(s) are also provided for storing virtual processors in virtual memory.

Abstract: A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream from each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. The logic network illustratively is an array of AND gates that tests each alignment unit to determine if it has detected a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.