Patents Assigned to Third Dimension Semiconductor, Inc.
  • Patent number: 7759204
    Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: July 20, 2010
    Assignee: Third Dimension Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
  • Patent number: 7015104
    Abstract: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region of at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from said top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanting into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: March 21, 2006
    Assignee: Third Dimension Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6936867
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 30, 2005
    Assignee: Third Dimension Semiconductor, Inc.
    Inventor: Xingbi Chen