Abstract: A multiplexer system includes a multiplexer (20) having plural inputs (1-K) and an output (15); plural channel processors (10) each having a control input, a data input for receiving an input signal, a complexity output for providing a signal representing the complexity of an associated input data signal, and a data output for providing a constant bit rate data signal to an associated input of the multiplexer; and a bit rate allocator (30) responsive to the complexity representing signals for providing bit rate control signals to the associated control inputs of the channel processors (10) as a function of the complexity representing signals, such that a bit rate of an output data signal from a channel processor (10) is a function of the complexity of an associated input data signal and to the combined of the input data signals.