Abstract: The present invention concerns a method and associated apparatus for reclaiming storage space on a personal video recorder using scalable video coding. When the personal video recorder reaches a storage threshold, enhancement layers of lower priority recordings may be removed to reduce the storage 5 space required for continued storage of those recordings. Various priority schemes may be utilized to determine which recordings should undergo layer removal, and which layers should be removed.

Abstract: A method for symbol synchronization of received digital signal and a digital signal reception apparatus are provided. The method comprises steps of correlating the received digital signal with the received signal delayed by one symbol so as to obtain a first correlation value result as a combined effort of a strongest path and other paths; removing substantially effect of the strongest path from the first correlation result so as to obtain a second correlation result which exhibits contribution of a fastest path; searching a maximum correlation value and its position of the fastest path so as to determine symbol synchronization timing for initiating FFT processing. The digital signal reception apparatus is characterized by a symbol timing detecting unit for determining symbol synchronization timing of the fastest path through substantially removing the effect of a strongest path.

Abstract: A system such as a multicast VOD system communicates content, e.g., delivers content or receives content, responsive to a user request for content and according to a schedule adapted to a user-specified acceptable latency for content delivery. The schedule may be modified to minimize initiation of delivery of content in response to the user's request. The schedule may also be modified to delay delivery of subsequent portions of the content as late as possible to allow subsequent requests to share a content stream while not exceeding the acceptable latency parameter specified by the user.

Abstract: A Wireless Regional Area Network (WRAN) receiver comprises a transceiver for communicating with a wireless network over one of a number of channels, and a signal detector for use in forming a supported channel list comprising those ones of the number of channels upon which an Advanced Television Systems Committee (ATSC) signal was not detected. The WRAN receiver performs a method comprising the steps of: dividing a total observation time looking for an ATSC data segment sync signal into multiple slices; computing at least one statistic for each slice; computing at least one overall statistic from the statistics computed for each slice; determining if the at least one overall statistic is greater than a threshold; and if the overall statistic is greater than the threshold, determining that an ATSC signal is present, otherwise, determining that an ATSC signal is not present.

Abstract: A direct conversion tuner for tuning either analog or digital television signals includes a first and second channels, each having first and second mixers and an intervening filter stage, coupled between an RF input and an output combining unit. The first mixers receive respective first local oscillator signals which have the same frequency but a quadrature phase relationship. The frequency of the first local oscillator signals is controlled according to the selected channel so that it is located within the spectrum of the respective RF signal. The second mixers receive respective second local oscillator signals which have the same frequency but a quadrature phase relationship. The frequency of the second local oscillator signal is located above the passband of the filter stages.

Abstract: A tuner includes a conversion (or heterodyning) stage, including a local oscillator and a mixer, for converting an RF signal corresponding to a selected channel to an IF signal. The local oscillator has only one tunable oscillating portion for generating a signal, and a frequency converter, such as a controllable frequency divider, for converting the frequency of the signal generated by said oscillating portion, so that the receiver is able to tune through the UHF and VHF bands. The operation of the requency converter is responsive to a digital controller, such as a microprocessor.

Abstract: A television receiver comprising a video display with a wide width to height ratio, horizontal and vertical deflection circuits for generating selectable rasters of different sizes on the video display by modifying horizontal deflection signals, a circuit (Rs) responsive to a vertical deflection signal and generating a first control signal, a waveform generator responsive to the first control signal and generating a substantially parabolic signal, a raster distortion correction circuit responsive to the substantially parabolic signal, and a source of a second control signal indicative of a selected horizontal raster width and the horizontal deflection being modified responsive to the second control signal.

Abstract: A Videocassette Recorder including VPS (Video Program System) and VPT (VCR Programmed by Teletext) automatic programming capability continuously compares preprogrammed VPS data to incoming VPS time codes for the currently running program, and to VPS program schedule information. In this way, the VPS and VPT controller in the VCR can detect errors in the original schedule pages from which it was programmed, and correct for those errors in its own record programming memory. Moreover, circuitry according to the subject invention can detect an error in the VPS code of a currently-running television show, correct for the error, and properly record the show.

Abstract: A sample of the high voltage retrace pulse is modeled across the series connection of a coil and low voltage winding of the flyback transformer. The AC current of the high voltage winding is fed through the coil in order to obtain the same retrace voltage shape as across the high voltage winding. Thus in this manner modeled high voltage retrace pulse is rectified by a diode and a charge capacitor. The rectified voltage is loaded by the beam current by a load resistor. The loading produces excellent tracking between the high voltage and the high voltage sample.

Abstract: A circuit presented automatically controls sound level. Sudden peak signal levels are controlled with a fast time constant of response and the overall sound level is controlled with a slower time constant of response. The feature can be enabled or disabled by the user via a microprocessor responsive to a remote control.

Abstract: A filtering method and apparatus in which an input signal is subjected to an analog filtering step, then an analog to digital conversion step and finally a digital filtering step to produce a filtered output signal. The pulse response of the digital filter is the mirror image of the pulse response of the analog filter and the cascaded filtering steps result in a filtered output signal which exhibits little or no group delay or phase distortion. The digital filter may be a FIR filter. Also disclosed is a phase error correction method whereby a pulse is inserted into a circuit or data stream prior to a group delay imparting device or function, a pulse response of the group delay imparting device or function is measured prior to a phase correcting device or function, mirror image filter coefficients are calculated using a window function and then incorporated into a phase correcting filter arrangement.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (.DELTA.) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal.

Abstract: A method and apparatus for scaling the bitstream of a compressed video signal includes partial decoding hardware (38, 41) to permit excising of higher frequency AC DCT coefficients or re-quantizing quantized data with a coarser quantization factor. The scaling is performed on a block (macroblock) basis in a manner which linearly scales the amount of compressed data per block. An analyzer (40) generates a profile of cumulative partially decompressed data over a video frame, and bitstream scaling (42) is performed in a manner which insures that a profile of the scaled signal substantially comports with the profile of the original data.

Abstract: A system of the present invention addresses the difficulty of aligning a reference sync byte at the beginning of a data packet during situations where the system experiences severe problems such as arbitrary resets/restarts or transmission disturbances. Specifically, the sync byte at the beginning of the data packet is automatically aligned with the beginning of a data acquisition interval when data is requested, even when there are arbitrary system resets/restarts. The alignment of the first data packet following a system reset is facilitated by the use of a Start Of Packet flag concurrent with the reference byte, together with a controlled logic network.

Abstract: An East-West switching transistor is coupled between a flyback transformer primary winding and a horizontal deflection output transistor circuit to control retrace energy to obtain an East-West modulation of the deflection current amplitude as required for East-West pincushion raster correction. A pair of series coupled first and second capacitors forming a capacitive voltage divider are coupled to a retrace resonant circuit that includes the deflection winding via a sampling switch, during a first half of a retrace interval, to produce a first ramping capacitor voltage in the first capacitor from a portion of a retrace pulse voltage. The first capacitor is coupled to an East-West pincushion raster correction current source for producing a second ramping capacitor voltage in the first capacitor that ramps in an opposite direction. A comparator is responsive to the capacitor voltage for controlling a conduction interval of the East-West switching transistor.

Abstract: An amplifier (60) provides an amplified video signal in response to a video input signal supplied thereto. A cathode current sensor (Q3), couples an output of the amplifier to the cathode of a kinescope (20) and also provides an output current (Ik) proportional to the kinescope cathode current. A feedback path (82) applies a portion of the sensed cathode current provided by the cathode current sensor to a circuit node (65 or 63) in the amplifier for imparting gamma correction to images produced by the kinescope. In one application the cathode current is apportioned (Q3, Q5) to provide gamma correction for the kinescope and to provide automatic kinescope bias (AKB) control.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format with a one dimensional data constellation includes a first carrier recovery network (18), an equalizer (20), and a second carrier recovery network (22, 30, 62). A multiple stage quantizer network (50, 66) exhibiting progressively finer resolution is associated with the operation of the equalizer for providing blind equalization without need of a "training" signal. The second carrier recovery network includes a phase detector (30) wherein a one symbol delayed (312) input signal and a quantized (310) input signal are multiplied (316), and an unquantized input signal and a quantized (310) one symbol delayed (314) input signal are multiplied (318). Signals produced by the multiplication are subtractively combined (320) to produce an output signal representing a carrier phase error.

Abstract: A transmission processor (16) receives an input packetized datastream (FIGS. 6-9; FIGS. 15-18 signal A) containing packets of data bytes including MPEG coded video information. The transmission processor outputs a symbol datastream (FIGS. 15-18 signal F) representing a sequence of data fields (FIG. 1) comprising groups of data segments (X) with an associated field sync segment. The transmission processor inserts overhead information. e.g., FEC error coding information, into each data segment, and inserts the longer duration field sync overhead segment between groups of data field segments. The frequency of the transmission processor input byte clock (SC/2, FIG. 6; FIG. 15) an integer sub-multiple of an output symbol clock (SC) frequency. The input datastream exhibits constant uniform inter-packet data gaps and a constant uniform data rate, thereby facilitating the seamless insertion of the field sync overhead segment into the datastream without interrupting the datastream.

Abstract: A packet encoder includes various sources of data, a state machine and additional circuitry. The state machine provides an S-bit output signal. N of the output bits of the state machine, (N<S), are coupled to directly control a multiplexer without an intervening state decoder. The multiplexer combines data from the various sources into a packet signal.

Abstract: A higher order phase loop filter includes an integrator consisting of an adder (25) and a delay element (31) arranged in a feedback loop between the output port of such adder and one of its input ports. Signal to be filtered is applied to a second input port of the adder. A detector (30) is coupled to the output of the adder to detect limiting values, which, when detected, conditions the detector to reset the current value in the delay element of the integrator to a fixed value such as zero. Resetting the delay element momentarily lowers the order of the filter and speeds system response time in the presence of noise.