Abstract: A semiconductor memory device has first and second power terminals, a plurality of MOS transistors as memory cells, a plurality of word lines respectively connected to the gates of the MOS transistors, and a bit line connected to one end of the current path of each of the MOS transistors. The other end of the current path of each of the MOS transistors is selectively connected to either the first or second power terminal, in accordance with data to be stored.

Abstract: A signal output circuit device according to the present invention comprises a first MOS transistor whose conduction is controlled by the potential given to its gate terminal, and gives the high level potential that is supplied by a high level voltage source to the output terminal, a diode which is inserted between the high level voltage source and the first MOS transistor so as to have its forward direction in the direction from the high level voltage source to the first MOS transistor, a second MOS transistor whose conduction is controlled by the potential given to its gate terminal, and supplies the low level potential supplied by a low level voltage source to the output terminal, and a diode which is inserted between the low level voltage source and the second MOS transistor so as to have its forward direction in the direction from the second MOS transistor to the low level voltage source.

Abstract: A plurality of key switches are provided between each pair of external terminals. A logic circuit generates time-division signals sequentially. The logic circuits stops the generation of these time-division signals during a blanking period with a predetermined time duration, thereby to stop the through-current during this period. The plurality of time-division signals are input to a plurality of buffer circuits. The outputs of the buffer circuits are supplied to the external output. Detection circuits detect only the operated key switches on the basis of the time-division signals and the signals from the external terminals exclusively used for key signal inputting. A plurality of switch members are provided between each of the external terminals and the reference potential. These switch members are conductive during the blanking period to improve the drive capability for external load.

Abstract: A semiconductor integrated circuit which has a CMOS inverter formed of p- and n-channel MOSFETs, and a D-type n-channel MOSFET coupled at the gate to the output terminal of the CMOS inverter, having one end coupled to a high voltage terminal and the other end coupled to the drain of the p-channel MOSFET.

Abstract: An electrostatic discharge protection circuit is provided with a variable threshold for limiting the potential of an input signal having a given high or low voltage, and is adapted to an EPROM containing an input MOS transistor which is responsive to the input signal. The protection circuit is associated with an input terminal for receiving the input signal. The input terminal is coupled to the gate of the input MOS transistor. The protection circuit also includes a circuit element for limiting or suppressing the input signal potential at the variable threshold. The gate of the input MOS transistor receives the potential limited signal from the circuit element. The circuit element is responsive to a given threshold control potential. The variable threshold is enhanced by the given threshold control potential when a high-voltage input signal is applied to the input terminal.

Abstract: First and second current mirror circuits are provided to the first and second amplifying transistors, respectively. The output current paths of current mirror circuits constitute output current terminals, respectively, and the reference input current paths are connected to the collectors of the first and second transistors, respectively. The first current mirror circuit comprises third and fourth transistors and the second current mirror circuit comprises fifth and sixth transistors. The base of the third transistor of the first current mirror circuit and the base of the fifth transistor of the second current mirror circuit are connected to first and second reference potentials, respectively. The base of the fourth transistor of the first circuit and the base of the sixth transistor of the second circuit are connected to the collectors of the first and second transistors, respectively.