Abstract: A solid-state imaging device includes a pixel array where pixels are arranged in a matrix. Each of the pixels includes a photoelectric conversion unit configured to generate a signal charge based on incident light, and an element isolation layer having light-shielding properties and surrounding a periphery of the photoelectric conversion unit. The element isolation layers of adjacent ones of the pixels in a row direction and a column direction are isolated from each other. A charge storage layer and a charge trapping layer are provided in each of regions between the element isolation layers of the adjacent ones of the pixels in the row direction and the column direction. The charge storage layer stores the signal charge. The charge trapping layer reduces incidence of light on the charge storage layer.

Abstract: A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.

Abstract: A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.

Abstract: First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction.

Abstract: A solid-state imaging device includes a pixel array where pixels are arranged in a matrix. Each of the pixels includes a photoelectric conversion unit configured to generate a signal charge based on incident light, and an element isolation layer having light-shielding properties and surrounding a periphery of the photoelectric conversion unit. The element isolation layers of adjacent ones of the pixels in a row direction and a column direction are isolated from each other. A charge storage layer and a charge trapping layer are provided in each of regions between the element isolation layers of the adjacent ones of the pixels in the row direction and the column direction. The charge storage layer stores the signal charge. The charge trapping layer reduces incidence of light on the charge storage layer.

Abstract: A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.

Abstract: A solid-state imaging device includes a plurality of pixels two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes at least one shallow light receiving portion formed near a surface of the semiconductor substrate and at least one deep light receiving portion formed under the shallow light receiving portion. One or more of the shallow light receiving portions and the deep light receiving portion are connected to each other so as to form a second light receiving portion. The rest of the shallow light receiving portions forms a first light receiving portion. Excess electric charge in the first light receiving portion is discharged to the deep light receiving portion.

Abstract: A solid-state imaging apparatus includes photoelectric conversion regions arranged close to a surface of a semiconductor substrate and a recessed portion provided above each photoelectric conversion region in the semiconductor substrate. Further, the solid-state imaging apparatus includes a light transmissive film embedded in the recessed portion. With this configuration, the performance of the solid-state imaging apparatus is improved, such as improvement of sensitivity and reduction in color mixture.

Abstract: A solid-state imaging device includes a first semiconductor substrate, photoelectric conversion portions arrayed on the first semiconductor substrate and configured to convert incident light to charges, a charge storage portion configured to hold charges transferred from a corresponding one of the photoelectric conversion portions via a transfer transistor, and an interconnect layer stacked on the first semiconductor substrate and including a plurality of metal interconnects. The incident light enters the first semiconductor substrate from a back surface side that is an opposite side to the interconnect layer. The solid-state imaging device further includes a light absorbing film between the photoelectric conversion portions and the metal interconnects.

Abstract: An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

Abstract: The semiconductor device includes: a gate electrode on a semiconductor substrate via a gate insulating film; an offset drain layer in the semiconductor substrate on one side of the gate electrode; a drain layer on the offset drain layer; and a source layer in the semiconductor substrate on another side of the gate electrode. The semiconductor device further includes: a protective film covering the semiconductor substrate; a field plate on the protective film, and having a portion above the offset drain layer; and a field plug connected to the field plate and in the protective film and above the offset drain layer, in such a manner as to avoid reaching the offset drain layer.

Abstract: A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

Abstract: A plurality of pixels are two-dimensionally arranged on a semiconductor substrate. Each of the pixels includes: two photodiodes each generating charge by photoelectric conversion; first and second memories spaced apart from each other between the two photodiodes as viewed in cross section; a first readout gate reading charge from the two photodiodes to the first memory; and a second readout gate reading charge from the two photodiodes to the second memory.

Abstract: A solid-state imaging element includes a plurality of shallow light receivers that are arrayed two-dimensionally in the vicinity of the surface of a semiconductor substrate and a plurality of deep light receivers that are arrayed two-dimensionally below the shallow light receivers. The shallow light receivers include visible light image light receivers that photoelectrically convert visible light and infrared light and output signals, and infrared light receivers that photoelectrically convert the infrared light. The infrared light receivers include a first infrared light receiver that is used to correct the signals output from the visible light image light receivers to provide signals of visible light components in the visible light image light receivers and a second infrared light receiver that is connected to the deep light receivers to form a multilayer light receiver.