Patents Assigned to Transmeta Corporation
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Publication number: 20150145580Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.Type: ApplicationFiled: December 30, 2008Publication date: May 28, 2015Applicant: TRANSMETA CORPORATIONInventors: Godfrey P. D'Souza, Keith Klayman
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Patent number: 7562233Abstract: Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficients of a quadratic approximation of a frequency-voltage characteristic of the microprocessor for a set of body biasing conditions. An efficient voltage for operating the microprocessor at the desirable operating frequency is computed. The microprocessor is operated at the efficient voltage and the set of body biasing conditions.Type: GrantFiled: June 22, 2004Date of Patent: July 14, 2009Assignee: Transmeta CorporationInventors: Eric Chen-Li Sheng, Matthew Robert Ward
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Publication number: 20090079460Abstract: An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT), a first ring oscillator, a second DUT and a second ring oscillator. The first DUT is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT. The second device under test is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator.Type: ApplicationFiled: November 24, 2008Publication date: March 26, 2009Applicant: TRANSMETA CORPORATIONInventor: Shingo Suzuki
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Patent number: 7509504Abstract: Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.Type: GrantFiled: September 30, 2004Date of Patent: March 24, 2009Assignee: Transmeta CorporationInventors: Kleanthes G. Koniaris, Stephen Lee, Mark Hennecke
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Patent number: 7498846Abstract: A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.Type: GrantFiled: December 23, 2004Date of Patent: March 3, 2009Assignee: Transmeta CorporationInventor: Robert Paul Masleid
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Patent number: 7496868Abstract: A computer implemented method and system for converting schematic diagrams. The method includes accessing a first set of schematic diagrams, wherein the schematic diagrams represent an integrated circuit design to be realized in physical form. A plurality of a first type of circuit elements in the first set are converted into a second type of circuit elements. The conversion is implemented in accordance with a set of conversion rules. A second set of schematic diagrams representing the integrated circuit design and including the second type of circuit elements are then output.Type: GrantFiled: October 12, 2004Date of Patent: February 24, 2009Assignee: Transmeta CorporationInventor: Steven T. Stoiber
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Patent number: 7495466Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.Type: GrantFiled: June 30, 2006Date of Patent: February 24, 2009Assignee: Transmeta CorporationInventors: Scott Pitkethly, Robert P. Masleid
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Patent number: 7496727Abstract: A secure memory access system and method for providing secure access to Hyper Management Mode memory ranges is presented.Type: GrantFiled: December 6, 2005Date of Patent: February 24, 2009Assignee: Transmeta CorporationInventors: Christian Ludloff, Kurt Daverman, Andrew Morgan
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Patent number: 7495497Abstract: A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.Type: GrantFiled: May 9, 2005Date of Patent: February 24, 2009Assignee: Transmeta CorporationInventor: Robert Fu
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Publication number: 20090045846Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.Type: ApplicationFiled: July 28, 2008Publication date: February 19, 2009Applicant: TRANSMETA CORPORATIONInventor: Scott Pitkethly
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Patent number: 7478226Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.Type: GrantFiled: September 29, 2006Date of Patent: January 13, 2009Assignee: Transmeta CorporationInventors: Alexander Klaiber, Guillermo Rozas
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Patent number: 7472033Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.Type: GrantFiled: October 17, 2002Date of Patent: December 30, 2008Assignee: Transmeta CorporationInventors: Godfrey P. D'Souza, Keith Klayman
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Publication number: 20080313440Abstract: A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.Type: ApplicationFiled: July 22, 2008Publication date: December 18, 2008Applicant: TRANSMETA CORPORATIONInventors: John Banning, H. Peter Anvin, Robert Bedicheck, Guillermo J. Rozas, Andrew Shaw, Linus Torvalds, Jason Wilson
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Publication number: 20080303600Abstract: A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.Type: ApplicationFiled: August 19, 2008Publication date: December 11, 2008Applicant: TRANSMETA CORPORATIONInventor: Robert P. Masleid
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Patent number: 7463050Abstract: Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted device-by-device to achieve essentially the same junction temperature at each device.Type: GrantFiled: May 26, 2005Date of Patent: December 9, 2008Assignee: Transmeta CorporationInventors: Eric Chen-Li Sheng, David H. Hoffman, John Laurence Niven
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Publication number: 20080294868Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.Type: ApplicationFiled: May 27, 2008Publication date: November 27, 2008Applicant: TRANSMETA CORPORATIONInventors: Guillermo Rozas, Alexander Klaiber, H. Peter Anvin, David Dunn
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Patent number: 7456628Abstract: An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT), a first ring oscillator, a second DUT and a second ring oscillator. The first DUT is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT. The second device under test is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator.Type: GrantFiled: January 2, 2008Date of Patent: November 25, 2008Assignee: Transmeta CorporationInventor: Shingo Suzuki
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Patent number: 7451300Abstract: Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocessor, while speculation normally permitted for certain other operations is suspended. Accordingly, while the fault is dispatched, some speculation is permitted as opposed to suspending all speculation. As such, microcode that makes use of speculation can be written.Type: GrantFiled: July 15, 2003Date of Patent: November 11, 2008Assignee: Transmeta CorporationInventors: H. Peter Anvin, David Dunn
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Patent number: 7444471Abstract: A method and system for using external storage to amortize CPU cycle utilization, wherein translated instructions are stored in a storage medium and subsequently accessed on a subsequent execution of a non-native application in order to amortize CPU cycles used in generating the translated instructions.Type: GrantFiled: December 30, 2002Date of Patent: October 28, 2008Assignee: Transmeta CorporationInventors: Brian O'Clair, Dean Gaudet
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Publication number: 20080246110Abstract: Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.Type: ApplicationFiled: June 16, 2008Publication date: October 9, 2008Applicant: TRANSMETA CORPORATIONInventors: Robert P. Masleid, James B. Burr, Michael Pelham