Abstract: The excessive bit error rate detection algorithm operates in two modes: BURST mode and non-BURST mode. In non-BURST mode, an alarm state is entered if an error count exceeds a threshold within a set number of frames and exits the alarm state when the error count stays below a threshold for a set number of frames. In the BURST mode, the alarm state is not entered unless the error count exceeds the threshold two consecutive times and does not exit the alarm state unless the error rate remains below a threshold for two consecutive frame counts.

Abstract: Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO, determining the FIFO depth over time, determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. For a 28-byte deep FIFO, if the depth of a FIFO is 12-16 bytes, no pointer leaking is performed. If the depth is 0-4 bytes, an immediate positive leak is performed. If the depth is 24-28, an immediate negative leak is performed. If the depth is 5-11 bytes a calculated positive leak is performed. If the depth is 17-23 bytes, a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames).

Abstract: An apparatus for correcting imperfectly equalized bipolar signals includes a delay line having a reset control, an AND gate, and a one-shot multivibrator. The apparatus is used in conjunction with an adaptive equalizer with the output of the adaptive equalizer being coupled to the input of the apparatus of the invention. More particularly, the output of the equalizer is coupled to the input and reset of the delay as well as to one input of the AND gate. The output of the delay line is coupled to the other input of the AND gate. The output of the AND gate is coupled to the input of the one-shot multivibrator and the output of the one-shot multivibrator is the corrected signal. The delay line is approximately equal to the pulse width of an erroneous pulse which is expected from over-equalization. When the delayed signal is compared to the original signal via the AND gate, narrow pulses are removed from the signal.

Abstract: Methods for managing multiple queues of ATM cells in shared RAM while efficiently supporting multicasting include providing a common memory for storing ATM cells and for storing at least one pointer to each ATM cell stored, providing a management memory for storing an index to the pointers stored in common memory, a table for each multicast session, and an index to the free space in common memory. According to the presently preferred method, cells entering the switch are examined, placed in shared RAM, and a pointer to the RAM location is written in another location in the shared RAM. Table entries in management RAM are updated each time a cell is added to a queue. When a multicast session is begun, a multicast table is created with all of the addresses in the multicast session. When a multicast cell is received, the multicast session table is consulted and pointers to the cell are copied to queues for each address in the table.

Abstract: The apparatus includes a separate line side inlet queue for each GFR VC, a single network side outlet queue for all GFR VCs, a single network side inlet queue for all GFR VCs, a single line side outlet bulk processing queue with a post queue packet processor followed by separate line side outlet queues for each line, a network side outlet queue monitor, and a line side inlet queue controller. The network side outlet queue monitor is coupled to the line side inlet queue controller so that the network side outlet queue monitor can send messages to the line side inlet queue controller. According to one of the methods of the invention, the network side outlet queue monitor sends messages to the line side inlet queue controller directing the line side inlet queue controller to send data from the line side GFR queues based on the status of the network side outlet GFR queue. According to another method of the invention, the line to side inlet queue controller discards packets for a GFR VC if congestion is indicated.

Abstract: An ATM switch system has a plurality of input ports and output ports all having associated buffers, and a source traffic control system which includes a shared bus coupling the ports, and a switch controller or arbiter which controls the transfer of data among the ports via the shared bus. ATM cells placed on the shared bus include an internal destination address which designates the output port within the switch to which the ATM cell is destined. The switch controller monitors the internal destination addresses of the ATM cells, and increments a counter associated with the destination port when the destination corresponds, and decrements other counters which do not correspond to the destination. Accordingly, bursts for a particular output port causes the count of the associated counter to grow large; whereas frequent or long breaks cause the count to drop. The counts are compared to a high threshold which alerts the arbiter that the buffer of the output port being tracked is in danger of overflowing.

Abstract: A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N.times.32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles.

Abstract: An asynchronous data transfer and source traffic control system includes a bus master and a plurality of bus users coupled to a bidirectional data bus. The bus master provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users.

Abstract: Apparatus and methods for allocating shared memory utilizing linked lists are provided which are particularly useful in telecommunications applications such as ATM. A management RAM contained within a VLSI circuit is provided for controlling the flow of data into and out of a shared memory (data RAM), and stores information regarding a number of link lists and a free link list in the shared memory, and a block pointer to unused RAM locations. A head pointer, tail pointer, block counter and empty flag are stored for each data link list. The head and tail pointers each include a block pointer and a position counter. The block counter contains the number of blocks used in the particular queue. The empty flag indicates whether the queue is empty. The free link list includes a head pointer, a block counter, and an empty flag. Each memory page of the shared data RAM receiving the incoming data includes locations for storing data.

Abstract: An ATM destination switch includes an ATM layer device coupled to a physical layer device. The ATM layer device includes a ATM layer interface which receives incoming ATM cells, a processor which is typically with an associated translation RAM, and an ATM layer to physical layer interface. The processor decodes the incoming ATM cell to obtain a VPI/VCI, and provides additional routing information (session number) for the cell for multicast purposes. The cell with the additional routing information is forwarded to the physical layer device which has a header processor, a multicast indicator storage table, preferably in the form of a bit map, for storing output line indications by session number, and a plurality of ATM line output interfaces.

Abstract: A synchronizer for telecommunications signals includes a telecommunications interface for receiving bits of a telecommunications signal having a frame, an SRAM which stores bit-defined states for a plurality of bit locations in the frame, a state update lookup table for changing the states for a plurality of the frame bit locations of the SRAM based on a previous state and based on an incoming bit of the telecommunications signal, and frame location identification logic for determining the location of the overhead bit of the telecommunications signal frame based on the states of the plurality of bit locations. In a first embodiment, the SRAM is an x by y bit SRAM, where x equals the number of bits in the frame, and y is large enough so that the number of possible states .ltoreq.2.sup.Y.

Abstract: Apparatus and methods for retiming an STS-3 type signal are provided. The SPE of an incoming STS-3 type signal is demultiplexed into three STS-1 payloads and fed to three FIFOs, and a byte which is synchronous with the TOH is tracked through the three FIFOs to provide an indication of the FIFO depth. A frame count is also kept to track the number of frames since a last pointer movement. Stuffs or destuffs are generated based on the FIFO depth as well as based on the frame count, with a stuff or destuff generated as quickly as four frames from a previous pointer movement if the FIFO is close to full or close to empty, and less quickly (e.g., at thirty-two frames from a previous pointer movement) if the FIFO is only starting to empty or to fill. Where the STS-3 type signal is a STS-3C signal, the decision on whether to stuff or destuff is made with reference to all three depth measurement circuits as all the STS-1 payloads must be stuffed or destuffed together.

Abstract: An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO for receiving the data component of the STS-1 signal, a measuring circuit having an input clock related to the STS-1 signal and the output clock of the apparatus as inputs for effectively measuring the relative fullness of the FIFO, and a voltage controlled crystal oscillator (VCXO) for receiving a control signal from the measuring circuit and for generating the output clock of the apparatus in response thereto, where data in the FIFO is taken out of the FIFO as the DS-3 signal according to the rate of the output clock. The FIFO is preferably a byte wide RAM, and the measuring circuit is comprised of two counters, an XOR gate, and a low pass filter. One counter receives the apparatus output clock as its input, while the other counter receives a gapped STS-1 data payload input clock as its input.

Abstract: Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the components. The space switch is essentially a non-blocking switch matrix. The time switch is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer to a virtual tributary time indication based on the phase of the synchronous clocked output buses.

Abstract: A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size.