Abstract: The disclosure proposes bit-error-rate (BER) and symbol-error-rate (SER) estimation techniques and its application to incremental-redundancy and rate-adaptation for modern-coded hybrid-ARQ systems. In particular, BER/SER estimators are proposed based on iterative refinement of mixture-density modeling of the bit/symbol decision metrics. For hybrid-ARQ systems, rate-adaptation functions are proposed based on BER/SER estimators for failed transmissions. Methods are disclosed for code-rate selection based on successfully decoded blocks as well as incremental parity size selection for retransmission of failed blocks Techniques disclosed here apply to forward-error-correction codes employed for digital data communication systems.
Abstract: The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.
Type:
Grant
Filed:
February 16, 2005
Date of Patent:
June 7, 2011
Assignee:
Trelliware Technologies, Inc.
Inventors:
Keith Michael Chugg, Paul Kingsley Gray, Georgios Dimitrios Dimou, Phunsak Thiennviboon