Abstract: A CMOS dynamic content addressable memory (CAM), having N- and P-channel transistors aligned in stripes for high packing density. In a preferred embodiment, each cell has a four transistor XOR gate for comparing a stored data bit with a comparand bit. Packing density is improved by symmetrically arranging each pair of neighboring rows and each pair of neighboring columns. The device, being of CMOS construction, has an inherently low soft error rate.