Abstract: A method for optimized filling holes and manufacturing fine lines on a printed circuit board (PCB) carries out the two processes separately. The inner wall of the hole is metalized with reduced graphene oxide (rGO) and then electroplated to fill the hole with copper. The processes are individually performed and thus operating parameters are considered independently. As a result, the copper-plating fillings are evenly compact and the fine lines have square profiles.
Abstract: Non-conductive substrates, especially the sidewalls of micro/nano holes thereof are chemically modified (i.e., chemically grafted) by reduced graphene oxide (rGO). The rGO possesses excellent electrical conductivity and therefore the modified substrates become conductive, so that it can be directly electroplated. These rGO-grafted holes can pass thermal shock reliability test after electroplating. The rGO grafting process possesses many advantages, such as a short process time, no complex agent (i.e., no chelator), no toxic agents (i.e., formaldehyde for electroless Cu deposition). It is employed in an aqueous solution instead of an organic solvent, and therefore is environmentally friendly and beneficial for industrial production.
Type:
Grant
Filed:
June 2, 2017
Date of Patent:
January 28, 2020
Assignees:
NATIONAL CHUNG HSING UNIVERSITY, TRIALLIAN CORPORATION
Abstract: A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 ?m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.