Abstract: A digital receiver includes a tuner and a demodulator that obtains a modulated signal carried in a received analog signal. A digital-to-analog converter operates at a preselected fixed sampling rate on the modulated signal to produce a first sequence of digitized samples. The first sequence of digitized samples is processed by a digital rotator to frequency-and phase-correct the first sequence of digitized samples. A controllable digital filter processes the first sequence to produce a filter output including a second sequence of digitized samples at a symbol rate. The second sequence is processed to ascertain a symbol rate of the modulated signal. The controllable filter coefficients are automatically varied to accommodate changes in the symbol rate of the modulated signal, so that the sampling rate of the digital-to-analog converter need not change.

Abstract: A digital receiver includes a tuner and a demodulator that obtains the baseband signal carried in a received analog signal. A first sampler operates at a preselected fixed sampling rate asynchronous with the baseband component to produce a first sampler output. A controllable digital filter resamples the first sampler output to produce a filter output with a selectable resampling rate. The resampled output is time-position locked to the baseband signal epochs. The second sampling is processed to ascertain the symbol bit stream of the baseband signal. The controllable filter sampling rate is automatically varied to correspond to the symbol rate of the baseband signal, so that the sampling rate of the first sampler need not change. Initial signal acquisition is achieved by operating the receiver as a frequency spectrum analyzer. A single signal-carrying band is identified and demodulated, and a menu carried on a transport layer is read.

Abstract: In a system which encodes video data in response to an encoding clock, transmits the encoded video data with an encoder clock signal representing the encoding clock frequency, and decodes the video data in response to a decoding clock, system clock accuracy is maintained by adjusting the decoding clock frequency. In order to reduce buffer requirements and to prevent deterioration of video program presentation, the decoding clock frequency is adjusted by slewing only during composite video synchronization periods when composite video decoded from the encoded video stream is not being presented. The preferred video synchronization periods are the vertical blanking interval and the front porch period. Restriction of decoding clock rate adjustment to these periods ensures that decoding clock slew rate limits may be unrestricted, thereby avoiding noticeable effects in the video program presentations.