Abstract: A hardware pixel processing pipeline and a video processing instruction set accelerate image processing and/or video decompression. The pixel processing pipeline uses hardware components to more efficiently perform color space conversion and horizontal upscaling. Additionally, the pixel processing pipeline also reduces the size of its output data to conserve bandwidth. A specialized video processing instruction set allows further acceleration of video processing or video decoding by allowing receipt of a single instruction to cause multiple addition operation or interpolation of multiple pairs of pixels in parallel.

Abstract: A hard real time (HRT) thread scheduler and a non-real time (NRT) thread scheduler for allocating allocate processor resources among HRT threads and NRT threads are disclosed. The HRT thread scheduler communicates with a HRT thread table including a plurality of entries specifying a temporal order for allocating execution cycles are allocated to one or more HRT threads. If a HRT thread identified by the HRT thread table is unable to be scheduled during the current execution cycle, the NRT thread scheduler accesses an NRT thread table which includes a plurality of entries specifying a temporal order for allocating execution cycles to one or more NRT threads. In an execution cycle where a HRT thread is not scheduled, the NRT thread scheduler identifies an NRT thread from the NRT thread table and an instruction from the identified NRT thread is executed during the execution cycle.

Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

Abstract: The present invention provides a computer pipeline control mechanism enabling a nonstalling pipeline despite the presence of pipeline hazards. The present invention detects the presence of predetermined pipeline hazard conditions, cancels the thread which contains the instruction encountering such pipeline hazard and then recirculates the program counter of the instruction having hazards for re-execution. The present invention guarantees the deterministic execution of threads in a computer pipeline.

Abstract: A local area network includes computers and peripherals networked in a high-speed LAN with access to a WAN through a slower connection via a broadband modem. A LAN gateway device manages data traffic between the local computers and peripherals and between the LAN and the WAN. The LAN gateway device provides multiple features, such as wired or wireless links, security, firewall, NAT, DCHP, traffic management, and the like. Traffic management features include an automatic quality of service priority classification scheme. A quality of service module automatically assigns priorities to the data streams based on analysis of the data packets. Traffic shaping techniques control the LAN gateway upstream output and enable IP fragmentation of TCP packets according to measured upstream channel conditions. The traffic shaping techniques estimate available upstream data rate, available downstream data rate, and the size of datagrams being used on the network link.

Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.

Abstract: According to one embodiment of the present invention, an active management system for a SOHO network includes an active management agent module operating in a SOHO network device that maintains ongoing real-time communications with an active management console module at an active management personal computer in the SOHO network. A secured communications protocol defines the format of packets to communicate queries and responses between the gateway and the active management computer. The queries enable real-time active management functions including outgoing connection approvals, incoming connection approvals, user access authorization, automatic ALG suggestions, personal content filtering, status reporting, and traffic statistics reporting.

Abstract: A local area network includes computers and peripherals networked in a high-speed LAN with access to a WAN through a slower connection via a broadband modem. A LAN gateway device manages data traffic between the local computers and peripherals and between the LAN and the WAN. The LAN gateway device provides multiple features, such as wired or wireless links, security, firewall, NAT, DCHP, traffic management, and the like. Traffic management features include an automatic quality of service priority classification scheme. A quality of service module automatically assigns priorities to the data streams based on analysis of the data packets. A configuration access list can be provided with pre-configured priorities for some streams. Initially, all streams are given highest priority and subsequently the priority is automatically adapted to the results of the packet analysis.

Abstract: A system and method for implementing high speed input and output protocols in software using hard real time threads. The processor provides both high speed and deterministic performance. The hard real time threads execute enough instructions per clock cycle of the input and output protocol to regularly transfer data.

Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.

Abstract: A universal serializer/deserializer (“ser/des”) is disclosed that provides hardware implemented modules of those functions determined to be most applicable to a communications protocol. Functionality that is determined to be more unique for a given protocol is implemented in software. Accordingly, a universal ser/des is provided that is able to be used for a plurality of different protocols now known, and configured to communicate with protocols that may be developed in the future.

Abstract: A processor including a plurality of netpages to store packet data and a netbuf to index the plurality of netpages is disclosed.

Abstract: An apparatus and method to provide a data processing system with reduced average power consumption while maintaining fast interrupt handling, and/or selectively change clock frequency for accessing memory with various access speeds. In a first embodiment, the invention provides a method to deterministically change a clock frequency between a first clock frequency and a second clock frequency in a data processing system to process operations upon the occurrence of a condition. In a second embodiment, the invention provides a method to change the clock frequency of a data processing system to process operations upon the occurrence of a condition. In a third embodiment, the invention provides a clock divider circuit to produce a core clock signal. In a fourth embodiment, the invention provides a data processing system with a deterministically variable processor clock.

Abstract: A processor including a plurality of netpages to store packet data and a netbuf to index the plurality of netpages is disclosed.

Abstract: A circuit with reduced short current. A first pair of delay transistors separates a second pair of transistors and prevents short current from flowing through the second pair of transistors.

Abstract: A system and method for detecting multiple inputs, e.g., the asynchronous transition of a pin input or a synchronous input from the CPU, and enables either of the inputs to generate a wake up signal using a single clock signal. The invention also resolves conflicts between the multiple inputs while using the single clock signal.