Abstract: A method for fabricating a window ball grid array (WBGA) semiconductor package is provided. A substrate is prepared having a through opening and ball pads on a lower surface thereof. A chip is mounted over the opening of the substrate via an adhesive, with gaps not applied with the adhesive left between the chip and substrate. The chip is electrically connected to the substrate via bonding wires through the opening. A spacer is attached to the lower surface of the substrate and has a through hole and a recessed portion around the through hole. During molding, the spacer is clamped between the substrate and a mold, and the recessed portion is located between the ball pads and the opening, such that a resin material for forming an encapsulation body encapsulates the chip and flows through the gaps to encapsulate the bonding wires. The recessed portion holds resin flash therein.

Abstract: A semiconductor package and a method for fabricating the same are proposed. A chip has an active surface, and an opposing non-active surface. A plurality of conductive elements are mounted on the active surface and electrically connected to the chip. A first encapsulant is formed on the active surface of the chip, for encapsulating the active surface and conductive elements, wherein end portions of the conductive elements are exposed to outside of the first encapsulant, and adapted to be recessed in position with respect to an exposed surface of the first encapsulant. A plurality of conductive media are implanted at end portions of the conductive elements, allowing the chip to be electrically connected to an external device by the conductive elements and conductive media. A second encapsulant is formed on the non-active surface of the chip, and cooperates with the first encapsulant to provide mechanical strength for the semiconductor package.

Abstract: A light sensitive semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a chip carrier and encompassed by a dam, and an infrared filter is attached to the dam to hermetically isolate the chip from the atmosphere. An encapsulant is formed on the chip carrier and surrounds the dam, and a lens is supported by the encapsulant to be positioned above the infrared filter. This allows light to penetrate through the infrared filter and lens to reach the chip. Before forming the encapsulant and mounting the lens, the semi-fabricated package with the chip being hermetically isolated by the infrared filter and dam is subject to a leak test, allowing a semi-fabricated package successfully passing the test to be formed with the encapsulant and lens, so as to reduce fabrication costs and improve yield of fabricated package products.

Abstract: A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.

Abstract: A stacked multi-chip semiconductor package and a fabrication method thereof are provided. A chip carrier is formed with an opening for receiving a first chip therein, and a second chip is stacked on the first chip and over the opening, wherein the first and second chips are respectively electrically connected to the chip carrier by bonding wires. A first encapsulant is formed to encapsulate first chip and corresponding bonding wires, and a second encapsulant is formed around the second chip to encompass a cavity for receiving the second chip and corresponding bonding wires therein. A lid is attached to the second encapsulant for covering the cavity. This semiconductor package allows high integration and increase in operational performances by virtue of stacked multi-chip structure.

Abstract: A mold structure for package fabrication is proposed, and includes a top mold, a fixture and a bottom mold. The top mold is formed with at least an upwardly recessed portion; the fixture is formed with a plurality of downwardly recessed portions; and the bottom mold has a recessed cavity for receiving the fixture therein, and adapted to be engaged with the top mold, wherein a resilient member is disposed on an inner wall of the recessed cavity, and interposed between the fixture and the recessed cavity of the bottom mold, allowing the resilient member to provide a resilient force for properly positioning the fixture. By using the above mold structure, chips mounted on a substrate can be firmly supported in the mold structure without causing chip cracks during a molding process for encapsulating the chips.