Abstract: A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other.

Abstract: A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a first sub-fin and a second sub-fin protruding from a surface of the substrate. The first isolation structure is disposed in the semiconductor fin used for electrically isolating the first sub-fin and the second sub-fin. The first dummy structure is disposed on the first isolation structure and laterally extends beyond the first isolation structure along a long axis of the semiconductor fin, so as to partially overlap a portion of the first sub-fin and a portion of the second sub-fin.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A silicon oxide gap-filling process is described, wherein a CVD process having an etching effect is performed to fill up a trench with silicon oxide. The reaction gases used in the CVD process include deposition gases and He/H2 mixed gas as a sputtering-etching gas, wherein the percentage of the He/H2 mixed gas in the total reaction gases is raised with the increase of the aspect ratio of the trench.

Abstract: A polishing head with a floating knife-edge mechanism includes a base, a retaining ring secured to the base defining a pocket area beneath the base, and a lower assembly floating within the pocket area via a diaphragm seal. The lower assembly includes a disk-shaped support plate having a plurality of apertures distributed in a center region of the support plate, a clamp ring used to secure the diaphragm seal along a rim region of the support plate, and the floating knife-edge mechanism positioned between the rim region and the center region of the support plate.

Abstract: An ESD (electrostatic discharge) protection circuit is provided, which features a low triggering voltage and a low leakage current and is suitable for use with a multi-voltage power supply circuit to protect the internal circuitry of the multi-voltage power supply circuit against ESD stress. This ESD protection circuit represents a solution to the problem of a thinning oxide structure in a downsized IC device that would be no longer able to withstand large ESD-induced transient current. This ESD protection circuit is not only suitable for use with 0.18 &mgr;m technology, but also suitable for use with 0.15 &mgr;m or 0.13 &mgr;m technology, and nevertheless can provide a robust ESD protection capability to the multi-voltage power supply circuit.

Abstract: In the present invention, a method of forming multitude of growth rates of oxide layer on the surface of a substrate is provided. The method comprises providing a first oxide layer on the substrate. A photoresist layer is formed on the first oxide layer. The photoresist layer exposes a portion of the first oxide layer. The exposed portion of the first oxide layer is subjected to plasma fluoridation. Then the photoresist layer is removed. Again, the first oxide layer is removed and a second oxide layer is formed on the substrate.

Abstract: A mosaic picture processing apparatus and method is disclosed. The present invention includes a memory device for storing picture data, which include index data, pattern data, and pattern control data. A pattern coordinate generating device is used for generating a horizontal coordinate and a vertical coordinate. A mosaic device is used for generating a mosaic control signal. Next, the index data is read from the memory device in response to the horizontal coordinate, the vertical coordinate, and the mosaic control signal. Further, the pattern data is read from the memory device in response to the horizontal coordinate, the vertical coordinate, the index data, and the mosaic control signal.

Abstract: The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffusion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide.

Abstract: A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.