Abstract: The presently disclosed method and apparatus provides the sensing of an output voltage of a charge pump without applying a load to the output stage. In the charge pump the voltage change which occurs across a capacitor of a stage of the charge pump when the charge pump transfers charge to the next stage is proportional to the difference between the voltage at the output of the charge pump under load, and the voltage which will be developed at the output of the charge pump with no load. There is an interval in the timing of the charge pump cycle after the first stage capacitor has transferred its charge to a second stage capacitor where the high side of the first capacitor has not yet been connected to the line voltage. During this interval the charge pump undervoltage detection circuit measures the voltage at the high side of the capacitor and compares this measured voltage to a reference voltage.

Abstract: Leading-edge blanking circuits blank the leading edge of a current sense signal generated by sensing circuitry sensing the current through a switching field-effect transistor. A current sensor is employed to sense the magnitude of gate current being provided to the gate of the switching transistor by a driver circuit. A comparator indicates whether the sensed magnitude of the gate current exceeds a predetermined threshold current. A blanking circuit component, such as a transistor connected to ground, is also used. In one blanking circuit, the blanking component forces the current sense signal to zero when the comparator indicates that the gate current of the switching transistor exceeds the threshold current, and otherwise allows the value of the current sense signal to be determined by the current-sensing circuitry. In another blanking circuit, a latch is interposed between the comparator and the blanking component. The latch generates a blanking control signal to control the blanking component.

Abstract: A ring generator circuit provides both a ring signal and talk battery to a subscriber telephone line. The ring generator recognizes whether talk battery voltage or a ring signal voltage is required and supplies the right voltage without the use of external relays. A switching network is coupled to the primary of a transformer to generate AC power at the transformer secondary. The switches intermittently conduct current from a DC power source through the primary of the transformer at a frequency substantially greater than the ring signal. A rectifier circuit converts the generated AC power into DC power to be provided to the telephone line. A sampling circuit samples the AC power, and the sampled power is additively combined with the DC power from the rectifier to form a ring signal component whose frequency is equal to the difference between the sampling frequency and the AC power frequency.

Abstract: A charge balancing circuit incorporates a voltage threshold which determines when to initiate a charge balance mode in order to equalize the level of charge in at least two cells of a multi-cell battery pack. Charge balancing is initiated when the voltage level of a first cell reaches this second threshold. Charge balancing then continues by modifying the charges of the first balance cell and a second reference lesser charged cell until the voltage levels of the first and second cells are equal. A subsequent charge cycle will result in the cell with the greatest charge being balanced with another of lesser charge. In this manner, all of the cells of a multi-cell battery pack are charge balanced over the course of plural charge cycles.

Abstract: A controller for variable speed three-phase AC squirrel-cage induction motors in accordance with a volts-per-hertz control method is disclosed. Direct current ("DC") link current is employed to compensate for rotor slip. In particular, rotor slip is estimated and added to a speed reference command to compensate for changing loads. A direction input and speed reference command provide complete control over the induction motor.

Abstract: A brushless DC motor controller including a track and hold circuit responsive to the voltage at the motor centertap terminal and the voltage across at least one motor winding in order to determine the position of the rotor by detecting zero crossings of the back EMF of the unenergized winding in a manner having reduced susceptibility to noise. In one embodiment, the output of the track and hold circuit is interpolated to reduce the effects of pulse width modulation noise on rotor position detection. The drive signals controlling a plurality of electronically controlled switches which effect energization of the windings are chopped in order to control the speed of the motor. In one embodiment, the switch connected to a positive voltage is chopped when the sensed back EMF is positive and the switch connected to the negative voltage is chopped when the sensed back EMF is negative.

Abstract: A motor-winding driver circuit includes a high-side double-diffused metal-oxide-semiconductor (DMOS) field-effect transistor (FET) connected between a direct-current (DC) power supply node and a driver output node, and a low-side DMOS FET connected between the driver output node and ground. A high-side drive circuit and a low-side drive circuit regulate the driver output voltage to prevent a parasitic bipolar PNP transistor in the high-side FET from conducting, so that latchup is avoided. A parasitic N+/P-substrate diode in the low-side FET is also prevented from conducting. The low-side and high-side driver circuits have additional circuitry causing them to act as active clamp circuits during extreme over- or under-voltage conditions. A body-switching circuit connects the body of the high-side DMOS FET to the driver output node during normal operation, and connects the body to the DC supply node when the driver output voltage exceeds the DC source voltage.

Abstract: A power factor correction controller is disclosed which extracts RMS information from a rectified AC input line voltage signal using a sample and hold analog to digital conversion approach. The controller then processes a digital word representing the RMS information through the application of a programmable mathematical function. The result is converted to analog form and provided as an input to an analog multiplier. The controller also monitors the output load power of an isolated boost converter circuit and linearly reduces the overlap delay time of a MOSFET transition switch when the load power decreases.

Abstract: A voltage-to-current converter for use with a bandgap voltage reference circuit for providing a correction current to compensate for the adverse effects of temperature. In one specific embodiment, the voltage-to-current converter is used to provide output voltage curvature correction to the resident bandgap voltage reference circuit.

Abstract: A multiplexing power converter for use with a single inductor for providing multiple power outputs is disclosed. The multiplexing power converter includes first switching means for providing a first low resistance path for current to flow from a power source through an inductor so as to energize the inductor, and at least one second switching means for providing at least one second low resistance path for current to flow from the inductor so as to deenergize the inductor and provide an output current. Only one low resistance current path is provided at any one time.

Abstract: A power supply controller implementing frequency foldback and volt-second duty cycle clamp features. An oscillator timing capacitor is charged with a fixed current and is discharged with a fixed current when the output voltage is above a predetermined level and with a decreasing current when the output voltage falls below the predetermined level, so as to decrease the power supply operating frequency during short circuit or overload fault conditions. A volt-second duty cycle clamp circuit limits the duty cycle to a maximum value which is independent of the tolerance of a capacitor which sets the maximum duty cycle as a function of the power supply input voltage.

Abstract: An integrated circuit controller for a switching power converter implementing feed-forward and synchronization features. The controller IC has pins which permit dual functionality. The feed-forward feature is implemented with a supply voltage from an unregulated auxiliary winding which additionally powers the controller. The synchronization feature is implemented by coupling an external synchronization signal to a feedback pin of the controller IC to which a feedback signal from the output of the converter is also coupled.

Abstract: An apparatus and method for generating a low frequency AC signal such as a ringing voltage signal for a telephone subscriber interface unit or the like. The apparatus comprises an oscillator which drives a pair of counters whose outputs differ by a desired low frequency. The output of the first counter is fed to a controlled current source so as to excite a resonant tank circuit and thereby provide a high voltage sinusoidal signal. The output of the second counter drives a switch which samples the high voltage sinusoidal signal. An alias frequency is thus generated which is filtered by an output capacitor. The method comprises steps which follow directly from the above-described apparatus.

Abstract: A battery charger/monitor circuit for charging and/or monitoring a plurality of series-connected cells, including a voltage sensor for sensing the voltage across each of the cells to provide a high cell voltage signal proportional to the highest voltage across any of the cells and a low cell voltage signal proportional to the lowest voltage across any of the cells. The circuit is operable in a monitor mode or a charge mode. In the monitor mode, the cells are disconnected from a load if the low cell voltage signal decreases to a first predetermined level. The circuit includes a controller which provides a control signal in response to the high cell voltage signal, the low cell voltage signal and a current sense signal, for controlling the charging of the cells.

Abstract: A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. In one embodiment, the last resistor ladder, processing the least significant bits of the digital word to be converted, is a binary weighted resistor divider. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed.

Abstract: A synchronous step-down DC to DC converter includes a bootstrap capacitor monitored by a controller for maintaining a desired bootstrap voltage to drive a high side NMOS switch. The controller temporarily increases the duty cycle of the low side NMOS switch when the bootstrap voltage decreases below a predetermined level to maintain a minimum level of charge on the bootstrap capacitor.

Abstract: A low capacitance impedance emulator suitable for active conductor termination. The impedance emulator includes an emulating FET and a control circuit coupled to the gate of the emulating FET for maintaining the FET in a linear region of operation. The control circuit includes a control FET, an impedance setting resistor, and an amplifier. The control FET is driven in a closed-loop fashion so that the impedance of the control FET has a known relationship with respect to that of the resistor. The output of the amplifier controls the conduction of both the emulating and control FETs so that the emulating FET provides an impedance proportional to that of the control FET and thus, related to the impedance of the resistor. A disconnect feature is provided, whereby the impedance emulator is responsive to a disconnect signal for disconnecting the impedance provided by the emulating FET.

Abstract: A battery protector for providing overvoltage and undervoltage protection to one or more series-connected cells. The battery protector includes a voltage detection and comparison circuit, providing an overvoltage signal indicative of whether the voltage across any of the cells is greater than an overvoltage threshold level and an undervoltage signal indicative of whether the voltage across any of the cells is less than an undervoltage threshold level, and a switch connected in series with the current path between the cells and a charger and/or load. In one embodiment, the switch is a four-terminal FET and a bias control circuit is provided for selectively connecting the body region of the FET to ensure that current does not flow through the parasitic FET diodes.

Abstract: A solid state circuit breaker for use in electronic devices which may be connected to an active computer bus. In one embodiment the solid state circuit breaker includes a digital to analog converter by way of which digital control signals are used to set the value at which the circuit breaker determines that a fault condition exists. Fault time is measured from when the fault condition is detected, and when the fault time exceeds a predetermined value, the circuit breaker opens, thereby preventing current flow through the circuit breaker for a second predetermined amount of time. Once this second predetermined amount of time elapses, the circuit breaker again permits current flow, and if a fault condition is determined to continue to exist, the cycle is repeated.The circuit breaker also includes a current limiting portion which restricts current flow to a maximum permissible value should the current flowing through the circuit breaker attempt to exceed this maximum permissible value.

Abstract: A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed.