Abstract: A computer interface having time frame dependent functional designation of parallel port lines system. A communication cycle is established with a plurality of time frames for a group of parallel port lines. Discrete data bytes are transferred to and from a computer, during at least one of the time frames and data blocks are transferred, to and from the computer, during at least one other of the time frames. The designation of the parallel port lines is redefined during each of the time frames to accommodate the transfers to and from the computer of the discrete data bytes and data blocks. Discrete data bytes and data blocks to be sent and received are stored and this storing is conditioned as a function of the designation of the parallel port lines during each of the time frames.

Abstract: An improved address generator for generating address values for refresh, read and write functions in a dynamic random access memory (RAM). Whether a refresh, write column, write row, read column or read row RAM addressing operation is to be performed is first determined. A shift register for storing and shifting at least one of the address values for each of the RAM addressing operations has its output connected to the address port of the RAM. A bit is selectively added, in response to the determination of which RAM addressing operation is to be performed, to the output of the shift register and the added value is submitted to the input of the shift register. A controller causes a data shift in the shift register at least once each time a bit is added to the value of the output of the shift register.