Abstract: A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.

Abstract: A capacitor is formed by providing a substrate, which has conductive structures with cap layer formed thereon. A first dielectric layer is formed over the substrate and the conductive structures. The first dielectric layer is patterned to form an opening to expose the substrate between the conductive structures and the sidewalls of the conductive structures. A conductive plug fills the opening. A second dielectric layer is formed over the first dielectric layer and the conductive plug. The second dielectric layer is patterned to form a narrow opening to expose the conductive plug. A conductive bar is formed to fill the narrow opening. The second dielectric layer is removed. A dielectric spacer is formed on the sidewall of the conductive bar. A conductive spacer is formed on the dielectric spacer. The conductive spacer has electric contact with the conductive plug. The dielectric spacer is removed by isotropic etching.

Abstract: A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high.

Abstract: The present invention relates to a dressing apparatus for conditioning and regenerating a chemical mechanical polishing (CMP) pad. More specifically, the invention relates to a diamond disc dresser that employs an air spraying assembly and radially arranged dressing tools to clean, flatten, and roughen the polishing pad. Each of the dressing tools points at a same radial angle but are not necessarily equidistantly separated. Furthermore, a debris collector is used to collect the micro-particles and other types of contamination after they are swept off the working surface of the polishing pad.

Abstract: A burst-mode capable RAM chip includes a timing circuit for clocking a burst counter during a burst transfer. In response to an input indicating the beginning of the burst transfer, the timing circuit generates a first signal that loads the initial address of the burst transfer into the latches of a burst counter. Then, the timing circuit generates a second signal to increment the burst counter to the second address in the burst transfer after the load of the initial address has successfully completed but prior to the second clock cycle. Finally, the timing circuit generates subsequent signals to increment the burst counter through the remaining addresses of the burst transfer. Each of the subsequent signals is generated in response to an input from the system clock.

Abstract: A type of wiring layout for pull-up and pull-down devices of an off-chip driver. This type of wiring layout is simpler and does not require the reservation of wiring space between neighboring bonding pads. Hence, layout area can be greatly reduced. In addition, even when the distance of separation between the pull-up device or the pull-down device and the bonding pad is great, no additional layout area is needed. Since the length of conductive wires for connecting to the pull-up or pull-down devices is much shorter, signal transmission speed is also increased.

Abstract: The memory cell, such as a DRAM, has a crown-shaped capacitor structure and is formed on a substrate having a first conductivity type (i.e., p-type) and preferably has the following structure. Portions of the substrate are doped to have a conductivity type opposite that of the substrate (i.e, n-type) to form drain and source regions. A gate is formed between the drain and source regions having a gate oxide adjacent the substrate, a first polysilicon region (Poly-1), tungsten silicide layer, and an oxide layer and SiyNx, respectively, on the gate oxide. SiyNx spacers cover the sides of the gate regions. Above the oxide layer are tetetraethylorthosilicate (TEOS) and borophosphosilicate (BPSG) layers. A second polysilicon layer (Poly-2) is patterned to form a bitline which contacts the source region. A layer of tungsten silicide, oxide, and SiyNx are formed on top of the bitline. SiyNx spacers surround the bitline. A crown-shaped capacitor contacts the drain region.

Abstract: A dynamic precharge redundant circuit for a semiconductor memory device. A PMOS transistor, a fuse, a first, second and third inverters, a first switch and a second switch are applied. A source of the PMOS transistor is coupled to a voltage supply, while a gate of the PMOS transistor is to receive a precharge signal. The fuse has a ground terminal and a terminal coupled to the drain of the PMOS transistor of which the drain is further coupled to an input terminal of the first inverter. The fuse is also coupled to a column address signal. The first inverter has an output terminal coupled to an input terminal of the first switch. The second inverter has an input terminal coupled to an output terminal of the first switch and an output terminal coupled to an input terminal of the third inverter, so as to output a bit-switch control signal.

Abstract: A process for fabricating a capacitor over bitline, DRAM device, using a self-aligned contact opening, through, and between the bitline structures, and featuring the formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, has been developed. The self-aligned contact opening, located through the bitline structures, allows an increase in DRAM cell density to be achieved. The formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, in a silicon oxide layer, allows silicon oxide to be used as the spacer material, thus resulting in capacitance decrease when compared to counterparts fabricated using silicon nitride spacers.

Abstract: A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is "turned off" to become non-conductive before the NFET that was non-conductive before the transition is "turned on" to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.

Abstract: A method of fabricating a DRAM. A substrate comprising a MOS is provided. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned to form a bit line contact window exposing a source region of the MOS and a node contact window exposing a drain region of the drain region simultaneously. The bit line window and the node contact window are filled with a bit line and a polysilicon plug by the formation of the same polysilicon layer, respectively. A second dielectric layer with an opening exposing the polysilicon plug is formed on the first dielectric layer. The sidewall and bottom surface of the opening are covered by another polysilicon layer. The second dielectric layer is removed to leave a node contact in contact with the polysilicon plug.

Abstract: A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC.

Abstract: A method of fabricating a dielectric layer which is application to be used in a capacitor. A first conductive layer is provided. A nitridation step is performed on the first conductive layer, so that a nitride layer is formed on a surface of the first conductive layer. A dielectric layer with a high dielectric constant is formed, followed by a thermal treatment and an oxygen plasma treatment to terminate dangling bonds of the dielectric layer. Consequently, oxygen is distributed on a surface of the dielectric layer and bonded with dangling bonds of the dielectric layer distributed on the surface.

Abstract: A method of fabricating a shallow trench isolation. A pad oxide and a dielectric layer are formed on a substrate. A trench is formed in the substrate penetrating through the pad oxide layer and the dielectric layer. The dielectric layer around the edge of the trench is removed to expose the substrate. The trench is filled to form a T-shaped insulation plug.

Abstract: A semiconductor mask has storage node patterns (101a, 101b, 101c, 101d) defining a first region and a second region. Serifs (10) are provided adjacent comers of the storage node patterns for reducing optical proximity effects. Diffraction bars (202) are positioned between the patterns in the first region. In alternative embodiments of the invention, a diffraction bar (702, 802) is situated adjacent patterns that are variously arranged and configured with respect to the diffraction bar.

Abstract: A circuit for disabling a two-phase charge pump includes a pump select circuit and a disable control circuit. The pump select circuit is configured to select one control signal from a plurality of control signals in response to at least one select signal. The selected signal is in effect provided to the disable control circuit, which also receives a pump disable signal. A voltage sensing circuit asserts the pump disable signal when the pumped voltage reaches a predetermined maximum level. While the pump disable signal is de-asserted, the disable control circuit in effect provides the selected signal to the two-phase charge pump as a pump control signal. However, when the pump disable signal is asserted, the disable control signal latches the current logic level of the pump control signal so that the pump control signal does not transition while the pump disable signal is asserted.

Abstract: The present invention provides a method of forming a tapered polysilicon contact plug having reduced dimensions beyond the normal resolution limit of a photolithographic method by utilizing at least one polysilicon sidewall spacer as a mask in an anisotropic etching process of an oxide layer such that a contact window of reduced dimensions can be formed for the subsequent deposition of a heavily-doped polysilicon for forming the contact plug.

Abstract: A method of forming cavities in a non-conducting layer on a semiconductor device is provided which can be carried out by first providing a pre-processed semi-conducting substrate which has a non-conducting layer and a patterned photoresist layer sequentially deposited and formed on top, and then conformally depositing a polymeric material layer on top of the non-conducting and the photoresist layer, and then etching the polymeric material layer to form polymeric sidewall spacers on the patterned photoresist layer, and then etching cavities in the non-conducting layer to expose the semi-conducting substrate. The polymeric sidewall spacers formed on the sidewalls of the photoresist openings allow the fabrication of cavities such as contact holes or line spacings of reduced dimensions while utilizing a conventional low cost photolithographic method for patterning.

Abstract: The present invention discloses a method of fabricating a multi-level interconnection on semiconductor substrate. A dielectric layer is formed on the substrate, and a first conductive layer is formed on the dielectric layer. An IMD layer is formed on the first conductive layer, a buffer layer is formed on the first IMD layer, a second conductive layer is formed on the buffer layer, and a second metal dielectric layer having a hole with a shallow trench is formed on the buffer layer. The width of the second conductive layer is the same with the width of the hole. A third conductive layer is formed, filling the shallow trench. The third conductive layer also contacts a sidewall of the hole and is accessible from the top of the second metal dielectric layer.

Abstract: A method for forming multilevel interconnects in a semiconductor IC device is provided. The method involves a simplified planarization process for planarization of inter-metal dielectrics that allows for easy and cost-effective fabrication of the device. By this method, an insulating layer is formed over a substrate, then a first conductive layer is formed over the insulating layer and which is selectively removed to form conductive interconnects. Subsequently, a dielectric layer is formed over the conductive interconnects. A photoresist layer is then formed and patterned over the dielectric layer by a spin-coating process. An etching process is then conducted on the photoresist layer and the dielectric layer with a 1:1 etching ratio until the photoresist layer is completely removed. At the same moment when the photoresist layer is completely removed, the via holes are formed. The following steps are the same for fabricating the next-level interconnects.