Patents Assigned to VeriSilicon Microelectronics (Shanghai) Co., Ltd.
-
Patent number: 11950066Abstract: The present disclosure provides a TWS earphone interaction method and system, and TWS earphones. When a main earphone and a secondary earphone receive a data packet sent by an audio source, within a residual slot of a data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining data transmission slot after the data packet is transmitted. When a data packet is received, the main earphone sends acknowledgment information to the audio source, within a residual slot of a next data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining of the next data transmission slot after the acknowledgment information is sent.Type: GrantFiled: June 22, 2021Date of Patent: April 2, 2024Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventor: Maogang Li
-
Patent number: 11783513Abstract: The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.Type: GrantFiled: July 19, 2021Date of Patent: October 10, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Mike M Cai, Yi Zhang, Yijun Li, Kui Qin
-
Patent number: 11693820Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.Type: GrantFiled: December 2, 2019Date of Patent: July 4, 2023Assignees: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventor: Yongliang Li
-
Patent number: 11647322Abstract: The present disclosure provides a TWS earphone communication method and system, and TWS earphones. The method includes: when an audio source sends a data packet and a main earphone correctly receives the data packet, the main earphone sends acknowledgment information in an acknowledgment information slot; when the data packet is incorrectly received by the main earphone, no information is sent in the acknowledgment information slot; and when the data packet is received correctly by a secondary earphone, the secondary earphone does not send any information in the acknowledgment information slot. When the data packet is not received correctly by the secondary earphone, it sends interference information in the acknowledgment information slot.Type: GrantFiled: June 22, 2021Date of Patent: May 9, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Shuai Li, Maogang Li
-
Patent number: 11600243Abstract: A display controller, comprising a 3D_LUT random access memory, which stores at least a 3D Lookup table; and a display control processing unit, comprising: a computing unit, a register, a color signal booster, and a color signal attenuator; wherein after input color signals are received by the color signal booster, and the color signal booster amplifies color signals by a first predetermined factor, wherein the computing unit calculates the address of the 3D Lookup table, and loads the 3D Lookup table from the 3D_LUT random access memory according to the register, wherein the color signal attenuator attenuates color signals by a second predetermined factor. The present disclosure significantly increases the precision of color conversion from one RGB color space to another RGB color space, and does not increase the RAM cost, since the cost of multiplying or dividing by power of 2, for example, is limited.Type: GrantFiled: August 16, 2021Date of Patent: March 7, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Lefan Zhong, Song Li, Jun Chen, Isaac Wang
-
Patent number: 11563407Abstract: The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.Type: GrantFiled: September 30, 2020Date of Patent: January 24, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Yu Li, Peng Ma, Yi Zeng, Shenglei Wang, Tony Qian
-
Patent number: 11557090Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.Type: GrantFiled: July 19, 2021Date of Patent: January 17, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
-
Patent number: 11557091Abstract: The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.Type: GrantFiled: July 19, 2021Date of Patent: January 17, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
-
Patent number: 11546682Abstract: The present disclosure provides a method and system for synchronous audio playback of TWS earphones, The TWS earphones include a master earphone and a slave earphone; both the master earphone and the slave earphone include a first timer, a second timer, an audio DAC, and an audio playback phase-locked loop; the first timer and the second timer of the master earphone are respectively used to collect a real-time audio playback position of the master earphone and a public Bluetooth clock; the first timer and the second timer of the slave earphone are respectively used to collect a real-time audio playback position of the slave earphone and a local Bluetooth clock; the slave earphone calibrates audio data in the audio DAC, and the first timer and the audio playback phase-locked loop of the slave earphone, to achieve synchronization between the master earphone and the slave earphone.Type: GrantFiled: June 22, 2021Date of Patent: January 3, 2023Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventor: Shuai Li
-
Publication number: 20220342474Abstract: The present disclosure provides a method and system for controlling peak power consumption, which dynamically controls frequency by monitoring the load in real-time, thereby reducing the power consumption, and providing sufficient computing performance while controlling peak power consumption. The method and system for controlling peak power consumption of the present disclosure monitor the load in real-time, and reduce power consumption by dynamically and intelligently controlling the operating frequency, to achieve a balance between performance and power consumption, such that the chip works at the highest frequency when the peak power consumption does not exceed the load threshold, thereby effectively improving the work efficiency while achieving the power consumption control.Type: ApplicationFiled: December 2, 2019Publication date: October 27, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventor: Huiming ZHANG
-
Patent number: 11455781Abstract: The present disclosure provides a data reading/writing method and system for in 3D image processing, a storage medium and a terminal. The method includes the following steps: dividing a 3D image horizontally based on the vertical sliding technology, the 3D image is divided into at least two subimages, a processing data of each subimage is stored in a circular buffer, after the subimage is processed, an overlapping portion data required by next subimage is retained in the circular buffer; dividing a multi-layer network of an image processing algorithm into at least two segments, the data between adjacent layers in each segment only interact through buffer, not through DDR.Type: GrantFiled: September 25, 2019Date of Patent: September 27, 2022Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Zhonghao Cui, Mankit Lo, Ke Zhang, Huiming Zhang
-
Patent number: 11301214Abstract: A circuit for performing multiply/accumulate operations evaluates a type of each value of a pair of input values. Signed values are split into sign and magnitude. One or more pairs of arguments are input to a multiplier such that the arguments have fewer bits than the magnitude of signed values or unsigned values. This may include splitting input values into multiple arguments and inputting multiple pairs of arguments to the multiplier for a single pair of input values.Type: GrantFiled: June 9, 2020Date of Patent: April 12, 2022Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Mankit Lo, Meng Yue, Jin Zhang
-
Publication number: 20220058838Abstract: The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.Type: ApplicationFiled: July 19, 2021Publication date: February 24, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Mike M CAI, Yi ZHANG, Yijun LI, Kui QIN
-
Publication number: 20220058867Abstract: The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.Type: ApplicationFiled: July 19, 2021Publication date: February 24, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng CHI, Jiangbo LI, Mike M CAI
-
Publication number: 20220028165Abstract: The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates.Type: ApplicationFiled: July 19, 2021Publication date: January 27, 2022Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventors: Cheng Chi, Jiangbo Li, Mike M Cai
-
Publication number: 20220004522Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.Type: ApplicationFiled: December 2, 2019Publication date: January 6, 2022Applicants: VeriSilicon Microelectronics (Chengdu) Co., Ltd., VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd., VeriSilicon Microelectronics (Nanjing) Co., Ltd.Inventor: Yongliang LI
-
Publication number: 20210400389Abstract: The present disclosure provides a TWS earphone interaction method and system, and TWS earphones. When a main earphone and a secondary earphone receive a data packet sent by an audio source, within a residual slot of a data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining data transmission slot after the data packet is transmitted. When a data packet is received, the main earphone sends acknowledgment information to the audio source, within a residual slot of a next data transmission slot, the main earphone and the secondary earphone can perform data interaction, wherein the residual slot is the remaining of the next data transmission slot after the acknowledgment information is sent.Type: ApplicationFiled: June 22, 2021Publication date: December 23, 2021Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventor: Maogang LI
-
Publication number: 20210400374Abstract: The present disclosure provides a TWS earphone communication method and system, and TWS earphones. The method includes: when an audio source sends a data packet and a main earphone correctly receives the data packet, the main earphone sends acknowledgment information in an acknowledgment information slot; when the data packet is incorrectly received by the main earphone, no information is sent in the acknowledgment information slot; and when the data packet is received correctly by a secondary earphone, the secondary earphone does not send any information in the acknowledgment information slot. When the data packet is not received correctly by the secondary earphone, it sends interference information in the acknowledgment information slot.Type: ApplicationFiled: June 22, 2021Publication date: December 23, 2021Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Shuai LI, Maogang LI
-
Publication number: 20210400367Abstract: The present disclosure provides a method and system for synchronous audio playback of TWS earphones, The TWS earphones include a master earphone and a slave earphone; both the master earphone and the slave earphone include a first timer, a second timer, an audio DAC, and an audio playback phase-locked loop; the first timer and the second timer of the master earphone are respectively used to collect a real-time audio playback position of the master earphone and a public Bluetooth clock; the first timer and the second timer of the slave earphone are respectively used to collect a real-time audio playback position of the slave earphone and a local Bluetooth clock; the slave earphone calibrates audio data in the audio DAC, and the first timer and the audio playback phase-locked loop of the slave earphone, to achieve synchronization between the master earphone and the slave earphone.Type: ApplicationFiled: June 22, 2021Publication date: December 23, 2021Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventor: Shuai LI
-
Patent number: 11163564Abstract: The present disclosure is directed to methods to generate a packed result array using parallel vector processing, of an input array and a comparison operation. In one aspect, an additive scan operation can be used to generate memory offsets for each successful comparison operation of the input array and to generate a count of the number of data elements satisfying the comparison operation. In another aspect, the input array can be segmented to allow more efficient processing using the vector registers. In another aspect, a vector processing system is disclosed that is operable to receive a data array, a comparison operation, and threshold criteria, and output a packed array, at a specified memory address, comprising of the data elements satisfying the comparison operation.Type: GrantFiled: October 8, 2018Date of Patent: November 2, 2021Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.Inventors: Charles H. Stewart, Charles R. Bezet