Patents Assigned to Vertest Systemsn Corp.
  • Patent number: 6137297
    Abstract: An interface module for testing integrated circuits and a method of manufacture are disclosed wherein a planar self supporting diaphragm supports signal paths connected to a pattern of probe contacts extending therefrom which are in registration with a pattern of integrated circuit access pads. The diaphragm is resiliently connected to a planar printed circuit board in a plane substantially parallel to the plane of the printed circuit board. A floppy substrate is placed between the printed circuit board and the diaphragm to provide signal paths from the printed circuit board to the self supporting diaphragm.The method includes laser location and drilling of holes to obtain a high density of accurately positioned small diameter holes in the self supporting diaphragm material to thereby accomplish high probe contact density in unlimited pattern arrays.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: October 24, 2000
    Assignee: Vertest Systemsn Corp.
    Inventors: Michael P. McNair, Louis H. Redondo, Nicholas M. Dimitropoulos, Donald A. Meirhofer