Abstract: A write buffer having selective flush is disclosed. The write buffer has address buffers and associated data buffers and comparators. During a "sneak read" operation, the address of the read operation is compared to the address signals stored in each of the address buffers. If a match is found, the read operation is temporarily suspended for only as long as the matched address remains stored in the write buffer. In a further improvement, the overhead associated with each match can be minimized to one write operation for each match before the matched address and data signals are written out of the write buffer.

Abstract: A GTL signal to CMOS level signal converter has a sense amplifier to receive the GTL signal and a clock signal and generate a first signal in response thereto. A buffer has a plurality of clocked stages for receiving the clock signal and the first signal and for generating the CMOS signal. A clock generates the clock and supplies the clock signal to the sense amplifier and the buffer.

Abstract: A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from two sources. The output of the master latch is coupled to the input of the slave and auxiliary latches. The clock driver circuitry receives a clock and control signals which are transformed into signals that operate the scannable latch in three different modes. In the normal mode, the slave latch is transparent and the data is held primarily in the master latch. In the scan mode, data may be shifted into the master, shifted out through the auxiliary latch, or shifted both in and out with a propagate function. Finally, in a test mode independent data values may be stored in the master latch and the slave latch.