Abstract: Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) comprises a user configurable element in the FPGA replaced by a mask configurable element in the ASIC. In a second aspect, an FPGA design conversion to an ASIC comprises converting a user configurable memory bit pattern generated by a software tool to program the programmable content of the FPGA to a hard-wired metal pattern for the ASIC.

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

Abstract: A programmable semiconductor device, wherein: a user programmable switch comprising a configurable element is positioned above a transistor gate material layer deposited on a silicon substrate layer.

Abstract: An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at least two inputs; and at least a one input and a two input response sequence, wherein the inputs change the output in a well defined response sequence; and a configuration circuit comprising one or more memory elements, wherein the memory bits are programmed to select one of said response sequences.

Abstract: A look up table (LUT) structure, comprising: a first intermediate LUT stage comprising a LUT value input and an output; and a configurable multiplexer (MUX) comprising: an input coupled to a carry in logic signal; and an output coupled to said LUT value input of first intermediate LUT stage; wherein, said first intermediate LUT stage output generates a carry out logic signal.

Abstract: Configuration circuits wherein configurable elements comprise low conducting on currents and/or low on to off current ratios for programmable logic devices are disclosed. A semiconductor device, wherein: a programmable logic circuit is configured by a control signal received at a capacitive node in the circuit, wherein the control signal is further generated by one of: a low conducting current pull-up configurable element configured to couple the control signal to a power supply voltage; and a low conducting current pull-down configurable element configured to couple the control signal to a ground supply voltage; wherein, the low conducting current charge the capacitive node to either the power or ground voltage levels.

Abstract: A configuration circuit, comprising: a configurable storage element coupled between a ground voltage and a first voltage, said storage element generating an output; and a voltage conversion circuit coupled between the ground voltage and a second voltage at a lower level than said first voltage, said circuit further coupled to said output; wherein, the voltage conversion circuit generates a configurable control signal either at the ground voltage level or the second voltage level by configuring the storage element.

Abstract: A three-dimensional semiconductor device, comprising: a programmable logic circuit constructed in a first module layer, said logic circuit input to output responses configurable to a user specification by configuring a plurality of control signals, each control signal received at a regulatory node in the logic circuit; and a configuration circuit constructed in a second module layer, said configuration circuit further comprising: a plurality of memory elements, each memory element having either one or two outputs, each memory element capable of storing one of two binary data values, each output coupled to one of said control signals, each control signal having either the same polarity of the stored memory bit or the opposite polarity of the stored memory bit; and a memory programming method to access each of said memory elements to alter the stored data value between said two binary data values to configure the control signals; wherein, the second module layer is positioned substantially above the first modul

Abstract: The present invention relates to electronic integrated circuits (ICs) that retain identical functionality with better performance or lower power dissipation under RAM and hard-wire ROM fabrication options, without the need to alter transistor layout within the IC. An integrated circuit (IC) comprising: a plurality of transistors; and a first selectable fabrication option comprised of a user configurable memory circuit; and a second selectable fabrication option comprised of a hard-wired circuit in lieu of said user configurable memory circuit; wherein, the IC functionality and performance is determined by the configuration memory data in the first fabrication option, and wherein the identical configuration is hard-wired in the second fabrication option without altering the location of transistors within the IC. Such a programmable to hard-wire conversion provides a significant IC cost reduction, performance improvement and power dissipation reduction at minimal NRE cost and improved reliability.

Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor thin film Gated-FET device, comprising: a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer, said gate region receiving a gate voltage comprised of: a first level that modulate said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said thin film layer in the channel region; and a second level that modulate said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate surface of the thin film layer in said channel region.

Abstract: A programmable semiconductor device wherein a programmable switch and a configuration element to program the switch are both positioned above a first metal layer.

Abstract: A layout of a programmable interconnect structure, comprising: an active region; and an even plurality of gate regions dividing the active region into a plurality of active stripes, said active stripes arranged into disjoint first, second and third sets; and a plurality of interconnect wires, each interconnect wire coupled to a contact in an active stripe of the first set; and an input wire coupled to a contact in each of the active stripes of said second set; and an output wire coupled to a contact in each of the active stripes of said third set; and a buffer layout comprising one or more buffer gate regions and one or more buffer active regions, wherein the input wire is further coupled to a buffer gate region and the output wire is further coupled to a buffer active region.

Abstract: A programmable look up table (LUT) structure of an integrated circuit, comprising: two or more LUT circuits, each said LUT circuit comprising: one or more inputs; and a plurality of LUT values; and at least one output; and a configurable multiplexer (MUX) circuit comprising: a plurality of inputs; and one or more select signals; and one or more outputs; wherein, the output of each said LUT circuit is directly coupled to a said input of the MUX circuit. Said structure further comprising one or more data storage units, each said data storage units comprising a digital output, wherein one or more of: a said MUX circuit input is directly coupled to a said data storage unit digital output.

Abstract: A programmable look up table (LUT) structure that offers higher logic packing capacity over conventional LUT structures for programmable logic devices is disclosed. A programmable LUT structure comprising a first stage and one or more intermediate stages and a last stage, wherein at least one of said intermediate stages or the last stage further comprises: a primary input received in true and compliment logic levels, and an output; and two LUT values, said primary input coupling one of said LUT values to said output, wherein at least one of said LUT values further comprises: a secondary input and a configurable data value; and a programmable means to select either the secondary input or the data value as the LUT value.

Abstract: A semiconductor device that provides identical functionality and timing characteristics, fabricated with two fabricating options comprised of: a user configurable high cost fabricating option utilizing a set of masking patterns and a process sequence; and a mask programmable lower cost fabricating option utilizing a reduced set of said masking patterns and reduced steps of said process sequence, wherein at least one mask is customized and a plurality of masks are identical.

Abstract: The present invention relates to electronic circuits that retain identical functionality and performance under RAM and hard-wire ROM fabrication options. An integrated circuit (IC) providing identical functionality and performance in two selectable fabrication options, wherein: a first selectable option comprises a user configurable circuit; and a second selectable option comprises a hard-wired circuit in lieu of said user configurable circuit. Such a programmable to hard-wire conversion provides a significant IC cost reduction at minimal NRE cost and improved reliability.

Abstract: A multiple input look up table (LUT) structure adapted for carry-logic implementation, wherein each input is received in true and compliment levels, comprising: an output of an intermediate stage within the LUT structure; and a LUT value input of a stage next to said intermediate stage; and a multiplexer (MUX) structure coupled between the output and the LUT value input, wherein the MUX structure further comprises: a plurality of secondary inputs, including a carry-in logic signal; and a configuration circuit to couple one of the output or a said secondary input to said LUT value input.

Abstract: A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.

Abstract: A mask configurable semiconductor device, comprising: a first module layer having a plurality of circuit blocks including at least one programmable logic block; and a second module layer deposited substantially above the first module layer, including a read only memory (ROM) configuration circuit to program said logic block to a user specification.

Abstract: A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable multiplexer comprising: a plurality of inputs and an output, wherein the inputs are coupled to said plurality of wires, and the output is coupled to said input of the buffer; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select one of said plurality of wires to couple to said buffer input; and a second programmable multiplexer comprising: an input and a plurality of outputs, wherein the input is coupled to said output of the buffer and the outputs are coupled to said plurality of wires; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select said buffer output to couple to o