Abstract: A rate adaptation system includes a barrel shift slot register and a rate adaptation register. The barrel shift slot register includes a plurality of slots with one of a valid read request or a dummy read request. A rate adaptation register is configured to sequentially cycle through the slots of the barrel shift register in response to a clock providing valid read requests to a FIFO buffer and to skip provision of valid read requests for clock cycles of the first clock associated with slots that include dummy read requests. The rate adaption register may also receive data blocks from the FIFO buffer and provide those data blocks to another FIFO buffer.

Abstract: A line driver circuit an method for protecting the line driver circuit from overdrive that includes generating an output signal for a transformer coupled to a load, and comparing a voltage of the output signal to a threshold voltage value. If the comparison indicates overload, the method further includes generating a control signal to reduce an amplitude of the output signal.

Abstract: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter.

Abstract: Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.

Abstract: Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.

Abstract: The present invention effectively cancels echo, near-end crosstalk and far-end crosstalk. A FEXT canceller is placed at the transmitter rather than at the receiver according to an aspect of the invention. In some embodiment, a FEXT canceller can be placed at the receiver only or the combination of both ends. The FEXT canceller is continuously adapted with information sent back from a remote receiver and with data from a neighbor transmitter that causes the crosstalk at the remote receiver. This allows the FEXT canceller to quickly adapt to a change in crosstalk function or conditions with the surrounding environment, for example, aging, temperature, humidity, physical pressure, etc. In some embodiments, an adaptation control signal is sent back from the receiver to the transmitter by using an overhead bit in the frame format. In some embodiments, part of the FEXT canceller is built-in at the remote receiver.

Abstract: Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.

Abstract: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter.

Abstract: An adaptive transversal filter having tap weights Wj which are products of corresponding tap coefficients Cj and tap gains Mj is provided. A filter control loop controls all of the tap coefficients Cj such that an error signal derived from the filter output is minimized. One or more tap control loops controls a tap gain Mk such that the corresponding tap coefficient Ck satisfies a predetermined control condition. For example, |Ck| can be maximized subject to a constraint |Ck| Cmax, where Cmax is a predetermined maximum coefficient value. In this manner, the effect of quantization noise on the coefficients Cj can be reduced. Multiple tap control loops can be employed, one for each tap. Alternatively, a single tap control loop can be used to control multiple taps by time interleaving.

Abstract: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter.

Abstract: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.

Abstract: Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.

Abstract: Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.

Abstract: A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first and second estimates of the phase error in a timing signal. A controller receives the first estimate and provides a signal to an NCO. An output from the NCO provides feedback to the error detector to complete a first order feedback loop, providing a first estimate phase error compensation. An integrator receives the second estimate and provides an output estimate for frequency offset of the timing signal that is received by the controller and the sign and magnitude of the integrated phase error are calibrated to provide a frequency offset. The controller determines a number of additional updates to the NCO required to minimize jitter and reduce word-length.

Abstract: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.

Abstract: An adaptive transversal filter having tap weights Wj which are products of corresponding tap coefficients Cj and tap gains Mj is provided. A filter control loop controls all of the tap coefficients Cj such that an error signal derived from the filter output is minimized. One or more tap control loops controls a tap gain Mk such that the corresponding tap coefficient Ck satisfies a predetermined control condition. For example, |Ck| can be maximized subject to a constraint |Ck|?Cmax, where Cmax is a predetermined maximum coefficient value. In this manner, the effect of quantization noise on the coefficients Cj can be reduced. Multiple tap control loops can be employed, one for each tap. Alternatively, a single tap control loop can be used to control multiple taps by time interleaving.

Abstract: A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.

Abstract: A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

Abstract: A 10GBASE-T clocking method that limits EMI and increases SNR, while reducing power and conserving chip space is provided. The method includes simultaneous clocking of transmitters in an analog front end of a 10 gigabit Ethernet. The method includes providing at least two channels to a 10GBase-T analog front end, where the channel has at least a transmitter port and a receiver port, and providing at least two phase interpreters to the analog front end, where each phase interpreter is dedicated to one receiver port. A central clock generator is disposed to distribute a transmit clock to the phase interpreters and to the transmitter ports, where the transmit clock is further provided to the receiver ports from the phase interpreters. Any clock delay between the clock generator and each channel is balanced and clock phases between the channels are matched.

Abstract: Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.