Patents Assigned to Violin Memory, Inc.
  • Publication number: 20120221922
    Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 30, 2012
    Applicant: Violin Memory, Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 8200887
    Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 12, 2012
    Assignee: Violin Memory, Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 8112655
    Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: February 7, 2012
    Assignee: Violin Memory, Inc.
    Inventors: Kevin D. Drucker, James H. Jones, Jon C. R. Bennett
  • Patent number: 8090973
    Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: January 3, 2012
    Assignee: Violin Memory, Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 8028186
    Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: September 27, 2011
    Assignee: Violin Memory, Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 7907069
    Abstract: A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: March 15, 2011
    Assignee: Violin Memory, Inc.
    Inventor: Matthias Oberdorfer
  • Patent number: 7877490
    Abstract: A method for efficient communications with a cluster-based architecture preserves various aspects of integrity throughout one or more connections with a client, even in the midst of connection migration between nodes in the cluster. According to one aspect, the invention provides a mechanism for preventing the loss of packets arising from a TCP connection migration within the cluster. According to another aspect, the invention provides a mechanism for uniquely identifying conflicting TCP connections migrated to a common node. According to a still further aspect, the invention provides a distributed TCP timestamp mechanism so that the sender and receiver will have a consistent view of the timestamp even when each node has different local clock values and regardless of how many times the socket has been migrated.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 25, 2011
    Assignee: Violin Memory, Inc.
    Inventors: Nisha Talagala, Qing Huang, Rama Chitta, Martin Patterson