Patents Assigned to VIOLIN SYSTEMS LLC
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Patent number: 11086519Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: GrantFiled: May 13, 2019Date of Patent: August 10, 2021Assignee: Violin Systems LLCInventors: Amit Garg, Timothy Stoakes, Vikas Ratna
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Patent number: 11010247Abstract: A memory system uses a dynamic RAID scheme to dynamically encode RAID address space geometries. The dynamic RAID scheme solves issues with the algorithmic layout approach and flat virtual address space used in conventional RAID systems. The dynamic RAID scheme can be used for any RAID algorithm and does not require static mapping. In other words, there is no requirement that each strip be located in the same relative location in memory devices and there is no requirement that stripes use the same combination of memory devices.Type: GrantFiled: May 24, 2019Date of Patent: May 18, 2021Assignee: VIOLIN SYSTEMS LLCInventors: Timothy Stoakes, Mark Lewis
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Patent number: 11010102Abstract: Efficient processing of user data read requests in a deduplicated data storage system places the metadata for most frequently requested data in data structures and locations in the system hierarchy where the metadata will be most rapidly available. The total amount of such metadata makes storing all of the metadata in high speed memory expensive, and the system and method described uses both the temporal and the spatial characteristics of the user system activity in any epoch to adjust the contents of metadata cache so as to respond to the dynamics of a multi user or multi-application environment where the storage system is not made aware of the time changing mix of operations except by observation of the individual requests. A history record is used to promote metadata from the slow memory to the fast memory, and a process selection may be adjusted based on the address-space activity.Type: GrantFiled: October 4, 2018Date of Patent: May 18, 2021Assignee: VIOLIN SYSTEMS LLCInventors: Amit Garg, Vikas Ratna
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Patent number: 11010076Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: GrantFiled: June 18, 2019Date of Patent: May 18, 2021Assignee: VIOLIN SYSTEMS LLCInventor: Jon C. R. Bennett
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Publication number: 20200371863Abstract: A memory system uses a dynamic RAID scheme to dynamically encode RAID address space geometries. The dynamic RAID scheme solves issues with the algorithmic layout approach and flat virtual address space used in conventional RAID systems. The dynamic RAID scheme can be used for any RAID algorithm and does not require static mapping. In other words, there is no requirement that each strip be located in the same relative location in memory devices and there is no requirement that stripes use the same combination of memory devices.Type: ApplicationFiled: May 24, 2019Publication date: November 26, 2020Applicant: Violin Systems LLCInventors: Timothy STOAKES, Mark Lewis
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Patent number: 10788988Abstract: A system and associated methodology for controlling block duplicates when deduplicating data (Dedup Blocks) to a storage space. The system includes a persistent database of known duplicates stored in the storage space (KD Table), and a non-persistent database of possible duplicates stored in the storage space (PD Table). Computer logic executes programming instructions stored in memory that are configured to index the KD Table according to a value derived from bits of a Dedup Block's hash signature, to index the PD Table according to another value derived by other bits of the Dedup Block's hash signature, to demote known duplicates from the KD Table to the PD Table, and to promote possible duplicates from the PD Table to the KD Table.Type: GrantFiled: May 24, 2017Date of Patent: September 29, 2020Assignee: VIOLIN SYSTEMS LLCInventors: Richard F. Lary, Bill Wong
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Patent number: 10754769Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.Type: GrantFiled: December 26, 2018Date of Patent: August 25, 2020Assignee: VIOLIN SYSTEMS LLCInventor: Jon C. R. Bennett
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Publication number: 20190303008Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Applicant: VIOLIN SYSTEMS LLCInventor: Jon C.R. BENNETT
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Patent number: 10417213Abstract: A storage system and method of operating the storage system is described where the metadata used to access the data stored in a storage device is distributed amongst a plurality of controllers in communication with a user, with each other and with the storage device. Each controller stores at least the metadata needed to access the data relevant to the user at the time, and metadata is updated to respond to internal system activities such as device failures, snapshots, backup operations or the like. To preserve coherence of the metadata, each metadata update is communicated to the other controllers and the storage device. The update is either transmitted to the other controllers and to the storage device and each metadata location is updated, or the update is transmitted to the storage device and each of the controllers is instructed to request an update from the storage device.Type: GrantFiled: January 19, 2016Date of Patent: September 17, 2019Assignee: VIOLIN SYSTEMS LLCInventors: Jagadish Kumar Mukku, Hector Cuellar
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Patent number: 10417159Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.Type: GrantFiled: April 17, 2006Date of Patent: September 17, 2019Assignee: VIOLIN SYSTEMS LLCInventor: Jon C. R. Bennett
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Patent number: 10409526Abstract: Data being stored in a block of flash memory system may be characterized as being frequently modified or infrequently modified (hot/cold) based on a heuristic. When performing garbage collection, if the data from hot blocks is consolidated and data from cold blocks is separately consolidated by writing the data to different free blocks, the number of write operations to perform the garbage collection may be reduced. The lower “write amplification” contributes to increasing the lifetime of the memory circuit. When the number of blocks in a pool of previously erased blocks is reduced to a threshold value, a block having data previously stored therein may be selected for garbage collection based on a second heuristic.Type: GrantFiled: December 10, 2015Date of Patent: September 10, 2019Assignee: VIOLIN SYSTEMS LLCInventor: Silei Zhang
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Publication number: 20190265893Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Applicant: Violin Systems LLCInventors: Amit GARG, Timothy Stoakes, Vikas Ratna
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Patent number: 10372366Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: GrantFiled: March 23, 2017Date of Patent: August 6, 2019Assignee: VIOLIN SYSTEMS LLCInventor: Jon C. R. Bennett
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Patent number: 10346045Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: GrantFiled: June 7, 2017Date of Patent: July 9, 2019Assignee: VIOLIN SYSTEMS LLCInventors: Amit Garg, Timothy Stoakes, Vikas Ratna
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Publication number: 20190129842Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Applicant: VIOLIN SYSTEMS LLCInventor: Jon C.R. Bennett
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Patent number: 10270705Abstract: A system and method for transmitting stateful data over a highly reliable stateless communications channel between a master device and a slave device is provided. Data that has been transmitted from the master device to the slave device is maintained in a buffer at the master device until the slave devices completes the actions required by commands accompanying the data and reports successful completion of the actions. Should an error occur in the data or processing of the data at the slave device an error message is sent from the slave device to the master device causing the stored transmitted data that has not as yet been acknowledged to be retransmitted to the slave device.Type: GrantFiled: December 15, 2014Date of Patent: April 23, 2019Assignee: VIOLIN SYSTEMS LLCInventors: Maxim Adelman, Stephen Fischer
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Publication number: 20190107953Abstract: Efficient processing of user data read requests in a deduplicated data storage system places the metadata for most frequently requested data in data structures and locations in the system hierarchy where the metadata will be most rapidly available. The total amount of such metadata makes storing all of the metadata in high speed memory expensive, and the system and method described uses both the temporal and the spatial characteristics of the user system activity in any epoch to adjust the contents of metadata cache so as to respond to the dynamics of a multi user or multi-application environment where the storage system is not made aware of the time changing mix of operations except by observation of the individual requests. A history record is used to promote metadata from the slow memory to the fast memory, and a process selection may be adjusted based on the address-space activity.Type: ApplicationFiled: October 4, 2018Publication date: April 11, 2019Applicant: VIOLIN SYSTEMS LLCInventors: Amit GARG, Vikas Ratna
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Patent number: 10248487Abstract: A method of managing a server is described where a service performed by a task executing on the server is configured into a plurality of sub-tasks, which may be further configured into a plurality of subsidiary tasks. When a subsidiary task executes, the completion thereof is determined to be either a successful or an unsuccessful completion. The completion status of the ensemble of subsidiary tasks is assessed on each completion of a subsidiary task, and the failure of any subsidiary task to successfully complete is deemed to be a failure to complete of the server task. The failure to complete is reported to the requesting application without waiting for the completion of any pending subsidiary task.Type: GrantFiled: January 21, 2016Date of Patent: April 2, 2019Assignee: VIOLIN SYSTEMS LLCInventors: Amit Garg, Vikas Ratna
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Patent number: 10228858Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: GrantFiled: August 14, 2017Date of Patent: March 12, 2019Assignee: VIOLIN SYSTEMS LLCInventors: Timothy Stoakes, Vikas Ratna, Amit Garg
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Patent number: 10204042Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.Type: GrantFiled: August 1, 2018Date of Patent: February 12, 2019Assignee: VIOLIN SYSTEMS LLCInventor: Jon C. R. Bennett