Abstract: A DMT/OFDM transceiver wherein communication occurs between stations in the form of symbols distributed and transmitted in channels which are allocated when making a link between the stations, each channel supporting a number of bits depending on the spectral response of the link when established. Instead of providing separate modules for performing iFFT's and FFT's, the transceiver has only a single FFT, or iFFT which operates on real and imaginary parts of the data stream; the outputs of the FFT or iFFT being supplied to a post processing stage where simultaneous equations having real and imaginary terms for the transmit and receive data, are solved in order to separate the transmit and receive data.

Abstract: A communication system comprises an input-output processor IOP (11) coupled to a plurality of network devices (10) and a protocol processor PP (12), both processors being coupled to a common memory (15). Memory access control means (16) resolves competition between the processors for memory access. Normally, if one of the two processors is accessing the memory, the memory control unit (16) allows that access to be completed before allowing the other processor to access the memory. But if data loss in a network device is imminent, the IOP, is granted a higher priority memory access, the memory access controller aborts (interrupts) any memory access by the PP, allowing the IOP to access the memory immediately.

Abstract: A session protection system for an ATM packet switching network enables real-time data to be protected from unauthorised access. The usual rules for transmission/reception ensure ATM cells are delivered in the order transmitted, and with a consistent VP or VP/VC value. ATM defines an adaptation layer for transmitting packets through a VC, whereby adaptation layer endpoints break packets into cells and packet transmission relies on both rules for correct operation. The session protection system disrupts this control and employs at least one pseudo random number generator (PRG1,PRG2), located in a transmitting network element (A) to break at least one of the rules by either delivering cells in a different order or delivering ATM cells with a non-consistent VP or VP/VC value. At least one pseudo random number generator (PRG1,PRG2) at a receiving network element (B) either reassembles cells in the order of transmission, or with a consistent VP or VP/VC value respectively.

Abstract: A cache controller is disclosed that includes a first means for determining when data specified by a memory address requested by the processor is absent from the cache, and a second means for determining when the processor reads sequential memory addresses. The second means is activated when the first means detects that data is absent from the cache and causes the cache controller to (i) permit data to be supplied from the main memory to the processor, even when the data is available in the cache; (ii) inhibit the first means from determining whether requested data is available in the cache; and (iii) update the cache with data supplied to the processor from the main memory.

Abstract: An ATM subnetwork, suitable for a low-cost home area network, comprises an interconnected mesh of simple ATM switches, end stations and multi-access buses implemented in fully-hardware configurations. Software for signalling and management functions does not reside in these devices, but rather is banished to computers outside the interconnected mesh. Specifically, an external controller acts a proxy for the simple ATM switches and performs all virtual channel connection set-up within the interconnected mesh. Additionally, proxy controllers manage each simple end station and proxy signalling agents permit standard ATM devices to be connected to the simple switches. These proxy processes communicate with the devices within the interconnected mesh via a control protocol of single cell messages delivered over dedicated permanent virtual circuits.

Abstract: A switching device for switching ATM cells from a plurality of network input links to a plurality of network output links comprises a plurality of ports containing line interfaces and input and output buffers, a hardware switch controller, a microprocessor, and memory for storing routing tables and system software. All these elements are interconnected via a processor bus, and additionally, the ports are interconnected by a separate switching bus. The switch controller employs hash-based routing table indexing to route cells from selected input ports to appropriate output ports according to the cells' header information. Switch requests generated by incoming cells are arbitrated using a token bus allocation scheme. The majority of cells are switched almost entirely in hardware, but the microprocessor can assume control of the switching architecture to resolve exception conditions and to perform special processing on selected virtual circuits.

Abstract: An ATM subnetwork, suitable for a low-cost home area network, comprises an interconnected mesh of simple ATM switches, end stations and multi-access buses implemented in fully-hardware configurations. Software for signalling and management functions does not reside in these devices, but rather is banished to computers outside the interconnected mesh. Specifically, an external controller acts a proxy for the simple ATM switches and performs all virtual channel connection set-up within the interconnected mesh. Additionally, proxy controllers manage each simple end station and proxy signalling agents permit standard ATM devices to be connected to the simple switches. These proxy processes communicate with the devices within the interconnected mesh via a control protocol of single cell messages delivered over dedicated permanent virtual circuits.

Abstract: A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a multi-functional timing ring which accommodates both preallocated static scheduling for use with CBR and real-time VBR virtual circuits, and dynamic scheduling for use with ABR, UBR, and non-real time VBR virtual circuits. The timing ring, in which cell transmissions are defined as actions, is processed sequentially in a burst fashion. Static actions are always performed at their allocated time intervals, so fixed transmission intervals can be guaranteed for CBR and real-time VBR traffic. Dynamic actions are moved from the timing ring to a latent queue, which permits dynamic actions to be performed during their scheduled time slot or during the first available time slot thereafter. This mechanism permits ABR and non-real-time VBR traffic contracts to be maintained.