Abstract: DC to DC converters are described that include two converters interconnected and operated to mitigate at least some of the effects of low duty cycle operation.

Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Abstract: Methods and structures for constructing a magnetic core of a coupled inductor. The method provides for constructing N-phase coupled inductors as both single and scalable magnetic structures, where N is an integer greater than 1. The method additionally describes how such a construction of the magnetic core may enhance the benefits of using the scalable N-phase coupled inductor. The first and second magnetic cores may be formed into shapes that, when coupled together, may form a single scalable magnetic core. For example, the cores can be fashioned into shapes such as a U, an I, an H, a ring, a rectangle, and a comb, that cooperatively form the single magnetic core.

Abstract: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

Abstract: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.

Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

Abstract: An integrated photovoltaic panel has one or more integral DC-DC converter circuits. The DC-DC converter input port couples to a section of at least one photovoltaic (PV) device of the panel separate from PV devices feeding other converters. The converter has an MPPT controller for operating the converter to transfer maximum power from coupled photovoltaic devices to its output port. The PV panel has a transparent substrate to which PV devices are mounted. A laminating material seals PV devices and converters to the substrate. In embodiments, the panel has multiple converters connected with output ports in series. The integrated PV panel provides summed maximum powers of each section of PV devices. In some embodiments the DC-DC converters are complete with inductors, in other embodiments a common inductor is shared by multiple converters of the panel, in a particular embodiment the common inductor is parasitic inductance of the panel.

Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

Abstract: An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.

Abstract: Various applications of interconnect substrates in power management systems are described.

Abstract: A multi-phase coupled inductor includes a powder core material magnetic core and first, second, third, and fourth terminals. The coupled inductor further includes a first winding at least partially embedded in the core and a second winding at least partially embedded in the core. The first winding is electrically coupled between the first and second terminals, and the second winding electrically is coupled between the third and fourth terminals. The second winding is at least partially physically separated from the first winding within the magnetic core. The multi-phase coupled inductor is, for example, used in a power supply.

Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.

Abstract: A voltage regulator is operated by determining whether a desired output current is below a threshold, and when the desired output current is below the threshold, generating a sequence of current pulses in a discontinuous current mode. A maximum current of the pulses is a function of the desired output current.

Abstract: A voltage regulator is operated by, during a finite period of a voltage regular start mode having a plurality of current pulses, monotonically increasing the maximum current of the current pulses and a target voltage.

Abstract: Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.

Abstract: A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: Methods and structures for constructing a magnetic core of a coupled inductor. The method provides for constructing N-phase coupled inductors as both single and scalable magnetic structures, where N is an integer greater than 1. The method additionally describes how such a construction of the magnetic core may enhance the benefits of using the scalable N-phase coupled inductor. The first and second magnetic cores may be formed into shapes that, when coupled together, may form a single scalable magnetic core. For example, the cores can be fashioned into shapes such as a U, an I, an H, a ring, a rectangle, and a comb, that cooperatively form the single magnetic core.

Abstract: Ripple cancellation techniques are described for various DC to DC converters having multiple parallel phases with magnetically coupled inductors.