Abstract: An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.
Abstract: A method and apparatus for determining a setting specified from a plurality of the settings for a function provided in an integrated circuit, wherein the setting is specified by connecting an external measurement resistor to a measurement terminal of the integrated circuit, comprises applying a direct current to the measurement terminal of the integrated circuit, thereby producing a measurement voltage at the measurement terminal; applying the direct current to a reference terminal of the integrated circuit, wherein the reference terminal has an external reference resistor connected thereto, thereby producing a reference voltage at the reference terminal; quantizing a voltage level of a difference voltage representing a voltage difference between the reference voltage and the measurement voltage, thereby producing a quantized voltage; and providing control signals to a functional module within the integrated circuit, the control signals representing the one of the settings corresponding to the quantized volta
Type:
Grant
Filed:
May 21, 2002
Date of Patent:
May 17, 2005
Assignee:
Volterra Semiconductor, Inc.
Inventors:
Jeremy M. Flasck, Andrew J. Burstein, David B. Lidsky, Michael D. McJimsey
Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.
Type:
Grant
Filed:
June 12, 2003
Date of Patent:
July 6, 2004
Assignee:
Volterra Semiconductor, Inc.
Inventors:
Lawrence T. Tse, Michael A. Davis, Anthony J. Stratakos