Patents Assigned to Western Digital
  • Publication number: 20240176501
    Abstract: A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files. This results in the logical address of one or both of the data fragments being continuous with the logical address of another data fragment of the same file. This logical address swap can take place without physically moving the data in the memory.
    Type: Application
    Filed: July 11, 2023
    Publication date: May 30, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Daniel J. Linnen, Ramanathan Muthiah, Judah Gamliel Hahn
  • Publication number: 20240177737
    Abstract: The present disclosure generally relates to a tape drive. The tape drive comprises a first tape head and a second tape head linearly aligned with one another, where the first tape head and the second tape head are configured to concurrently operate. The first tape head and the second tape head each comprise a plurality of write transducers, a plurality of read transducers, and a plurality of servo transducers. The tape drive further comprises a first actuator coupled to the first tape head and a second actuator coupled to the second tape head. The first and second actuators are configured to independently tilt and move the first and second tape heads, respectively. Tilting and moving the first and second tape heads individually enables the tape drive to compensate for non-linear tape dimensional stability effects.
    Type: Application
    Filed: February 8, 2024
    Publication date: May 30, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Junzo NODA, Robert G. BISKEBORN
  • Patent number: 11996145
    Abstract: Technology is disclosed for a memory system having a cross-point array with threshold switching selector memory cells. Each memory cell has a two-terminal threshold switching selector memory element that may be programmed to two different on-state conductances in order to store information. One bit value may be represented by a high-resistance state (HRS) when in the on-state and another bit value may be represented by a low-resistance state (LRS) when in the on-state. In one aspect, a conditioning signal is applied to the memory cell prior to programming. Applying a program signal with the opposite polarity as the conditioning signal may result in a higher conductance in the on-state than applying a program signal with the same polarity as the conditioning signal. The memory element may also serve as a selector for the memory cell. The memory element may include an Ovonic Threshold Switch (OTS).
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: May 28, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hans Jurgen Richter, Michael K. Grobis
  • Patent number: 11997364
    Abstract: Systems and methods for peer-to-peer video data transfer on demand from an edge data storage device to a browser are described. A media device, such as a surveillance video camera, may include a media server and a WebRTC peer application. The media server may send media stream files using a first data transfer protocol to the WebRTC peer application in the media device. Using a second data transfer protocol, the WebRTC peer application on the media device may establish a secure peer-to-peer connection to a connection handler on a user device. The connection handler on the user device may provide the media stream files to an internet browser on the user device and the internet browser may display the media from the media stream file using an HTTP Live Streaming (HLS) library.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 28, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vishwas Saxena, Mukesh Kumar P, Venkatesh Naidu Pamoti
  • Patent number: 11995327
    Abstract: A data storage device and method for adaptive host memory buffer allocation based on virtual function prioritization are provided. In one embodiment, a data storage device is provided comprising a memory, an interface, and a controller. The controller is configured to receive priority information of each of a plurality of virtual functions in the host and allocate space in the host memory buffer for each of the plurality of virtual functions based on the priority information. The controller is further configured to dynamically reallocate the space. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 28, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Judah Gamliel Hahn, Ariel Navon, Alexander Bazarsky
  • Patent number: 11995223
    Abstract: This disclosure relates to data storage device (DSD) hardware and, more specifically, to systems and methods for encrypting data stored on a DSD. A DSD comprises a non-volatile storage medium to store multiple file system data objects using block addressing. A device controller is integrated with the DSD and comprises hardware circuitry configured to encrypt data to be stored on the storage medium. The controller receives a request for an encrypted file system data object from a host computer system, identifies one of the ranges of blocks where the requested encrypted file system data object is stored on the storage medium, and sends the file system data object stored in the identified range of blocks to the host computer system in encrypted form as stored on the storage medium.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 28, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Matthew Harris Klapman
  • Publication number: 20240168801
    Abstract: The present disclosure generally relate to improved tenant processing by arbitration of commands. Rather than processing a tenant with multiple portions to completion causing increased wait time for preceding tenants, allowing the controller to process commands based on the respective bandwidth allocated to each tenant is beneficial. Through a Weighted Round Robin (WRR) arbiter, the controller is able to allocate a percentage of the bandwidth to each tenant based on the tenant's needs. Once the bandwidth is allocated to the tenants, the controller may then process portions of the commands from the tenants up to the allocated bandwidth per tenant, which avoids the need for commands that are fetched after earlier commands wait for previous commands to complete their processing, but instead process all command portions based on the allocated bandwidth from the WRR arbiter.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20240168683
    Abstract: A data storage device for providing zone management optimization may include memories including staging memory areas (e.g., single level cells) and destination memory areas (e.g., quad-level cells). The destination memory areas may include memory regions (e.g., zones). A controller may be configured to receive data from a host system, write the data initially to the staging memory areas, receive a region full indication for a first memory region. In response to receiving the region full indication, the controller may add a first entry corresponding to the first memory region to a double linked list. The controller may select, using a region selection randomization method, a second entry corresponding to a second memory region, and folds a second data to the second memory region. The first data may be associated with the first memory region and the second data may be associated with the second memory region.
    Type: Application
    Filed: July 13, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventor: Xiaoying LI
  • Publication number: 20240168644
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When data received by the controller, from a host device or from a non-volatile memory of the data storage device, the controller maintains table tracking the location of the data. The table may include a current location of the data in a volatile memory of the controller or the data storage device as well as the current location of the data a latch of the non-volatile memory. The table may further associate the location with a logical block address, such that when the host device requests the data not yet programmed to the non-volatile memory or data that is part of a data relocation operation, the controller may utilize the table to locate the relevant data and provide the data to the host device.
    Type: Application
    Filed: July 6, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Michael IONIN, Alexander BAZARSKY, Judah Gamliel HAHN
  • Publication number: 20240168684
    Abstract: A data storage device for providing efficient deallocation and reset of zones may include a host interface for coupling the data storage device to a host system. The data storage device may also include a controller. The controller may be configured to receive a format or reset zone command from a host system. The controller may also be configured to, in response to receiving the format or reset zone command, extract a time limit from the format or reset command. The controller may also be configured to, within the time limit: set a bitmap for a plurality of memory regions; and perform deallocation or reset of zones of at least a portion of the plurality of memory regions, according to the bitmap. The controller may also return a command completion to the host system.
    Type: Application
    Filed: July 13, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xiaoying LI, Hyuk-Il KWON
  • Publication number: 20240168682
    Abstract: A data storage device for providing failure recovery may include a device memory including one or more memories and a command history buffer. The device memory may be configured to receive and process (i) commands directed to the one or more memories, and (ii) an access command for accessing the command history buffer. The command history buffer may be configured to store information related to the commands. The data storage device may also include a controller coupled to the device memory and configured to: send the commands to the device memory; retrieve information stored in the command history buffer from the device memory, by issuing the access command; and in accordance with a determination that the information stored in the command history buffer indicates invalid command flows, resend at least a portion of the commands to the device memory.
    Type: Application
    Filed: July 13, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nataniel PEISAKHOV, Roman LIVSHITS, Natan TABACHNIK, Moshe KARNI, Maor KATZ, Paz BEN AHARON
  • Patent number: 11989431
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store data mappings in an uLayer, where the uLayer includes a plurality of mSet updates, and where the uLayer is organized into a sorted section and an unsorted section, sort one or more of the plurality of mSet updates of the uLayer, and provide, to a host device, data stored in the memory device corresponding to a most recent update of a data mapping by ignoring non-recent updates for a read command associated with an mSet group of the sorted section.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Moshe, Nava Eisenstein, Tomer Baron
  • Patent number: 11990162
    Abstract: The present disclosure generally relates to a tape head and a tape head drive including a tape head. The tape head comprises at least one same gap verify (SGV) module comprising a closure, a substrate, and a plurality of write transducer and read transducer pairs disposed between the substrate and the closure. The write transducer and the read transducer of each pair are aligned in a first direction and spaced a distance in the downtrack direction of about 5 ?m to about 20 ?m. A first overcoat is disposed over each write transducer at a media facing surface (MFS), and a second overcoat is disposed over each read transducer at the MFS. The first and second overcoats may comprise different materials, and are deposited during different processes.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: David J. Seagle, Robert G. Biskeborn
  • Patent number: 11989127
    Abstract: The present disclosure generally relates to improving space efficiency when storing logical to physical (L2P) entries. Rather than writing a physical block address (PBA) spanning multiple entries, the PBA is split between a first portion stored in the buffer with the remaining bits of the PBA added to the metadata buffer. The metadata buffer is sub-optimal due to the small size of the metadata relative to the entry and therefore, adding extra bits to the metadata buffer will make the metadata buffer more optimal. In this scheme, the alignment is preserved, the system becomes more optimal in terms of DRAM access, and the metadata buffer can be easily optimized and adapted.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11990164
    Abstract: The present disclosure is generally related to a tape drive comprising a tape head assembly. The tape head assembly comprises a spring adaptor, the spring adaptor comprising a first hole, a second hole, and a spring member disposed between the first hole and the second hole, a beam disposed within the first hole of the spring adaptor, a first module disposed on the beam, the first module comprising a first plurality of write transducers and a first plurality of read transducers, a second module disposed on the beam adjacent to the first module, the second module comprising a second plurality of write transducers and a second plurality of read transducers, and an actuator disposed in the first hole. The actuator is controllable to move the beam in a direction transverse to a media movement direction. The spring adaptor stabilizes the beam while the beam is being actuated.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kenji Kuroki, Oscar J. Ruiz, Eduardo Torres Mireles, Robert G. Biskeborn, Masahito Kobayashi
  • Patent number: 11989458
    Abstract: Technology is disclosed herein for handling of mixed random read and sequential read command sequences. Plane read commands are formed from one or more sequential read commands. A sequential read command may be split into multiple plane read commands at plane boundaries. The plane read commands are submitted to the respective planes as asynchronous independent plane read commands. Random read commands may be submitted to the planes as asynchronous independent plane read (AIPR) commands on par with the split sequential read commands. Therefore, AIPR may be used for both sequential read commands and random read commands. Submitting a split sequential read command to one or more planes while one or more other planes are performing a random read command can significantly improve performance.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dattatreya B Nayak, Ramanathan Muthiah
  • Patent number: 11990161
    Abstract: A data storage device is disclosed comprising a head actuated over an energy assisted magnetic media comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A write operation to a first data sector is executed by applying a first current to a write coil of the head while the head is over a second data sector preceding the first data sector, wherein the first current comprises a first amplitude. A second current is applied to the write coil while the head is over the first data sector, wherein the second current comprises a second amplitude lower than the first amplitude.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Joey M. Poss, Naoto Ito, Phillip S. Haralson
  • Patent number: 11990154
    Abstract: The present disclosure generally relates to data storage devices, comprising: a magnetic tape; a tape head configured to write data to and read data from the magnetic tape; a first reel having a first interior surface; a second reel, wherein the first reel and the second reel are configured to wind and unwind the magnetic tape; one or more motors configured to actuate the first reel and the second reel; a first magnetic recording surface disposed on the first interior surface of the first reel; an actuating arm disposed between the first reel and the second reel; an actuator coupled to a distal end of the actuating arm; and a magnetic recording head disposed on the actuating arm. The magnetic recording head being situated a distance away from the actuator, wherein the actuating arm is configured to move about the actuator such that the magnetic recording head is able to contact the first magnetic recording surface to write data to and read data from the first magnetic recording surface.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Akira Sakagami, Takehiko Hamaguchi, Keiichi Okada
  • Patent number: 11990163
    Abstract: Aspects of the present disclosure generally relate to magnetic recording heads (such as write heads of data storage devices) that include multilayer structures to facilitate targeted switching and relatively low coercivity. In one or more embodiments, a magnetic recording head includes an iron-cobalt (FeCo) layer having a crystalline structure that is a cubic lattice structure, a first crystalline layer formed of a first material, and a second crystalline layer between the first crystalline layer and the FeCo layer. The second crystalline layer is formed of a second material different from the first material, and the second crystalline layer interfaces both the FeCo layer and the first crystalline layer. The crystalline structure of the FeCo layer has a texture of <100>.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ning Shi, Brian R. York, Susumu Okamura, Suping Song
  • Publication number: 20240161777
    Abstract: A heat-assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole with a pole tip at the GBS. The pole tip has a narrow cross-track width that can be substantially the same as the cross-track width of the NFT output tip. A plasmonic layer is located between the main pole and the NFT and has a tip at the GBS between the main pole tip and the NFT output tip. The plasmonic layer may also be located on the cross-track sides of the main pole and the main pole tip.
    Type: Application
    Filed: May 23, 2023
    Publication date: May 16, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventor: Takuya MATSUMOTO