Abstract: A semiconductor structure for improving the thermal stability and Schottky behavior by engineering the stress in a III-nitride semiconductor, comprising a III-nitride semiconductor and a gate metal layer. The III-nitride semiconductor has a top surface on which a conductive area and a non-conductive area are defined. The gate metal layer is formed directly on the top surface of the III-nitride semiconductor and comprises a gate connection line and at least one gate contact extending from the gate connection line in a second direction perpendicular to the length of the gate connection line. The at least one gate contact forms a Schottky contact with the III-nitride semiconductor on the conductive area, and the gate connection line is in direct contact with the III-nitride semiconductor on the non-conductive area. The non-conductive area of the III-nitride semiconductor is at least partially covered by the gate connection line.

Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.

Abstract: A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to ?5×107 dyne/cm2 and less than or equal to 5×107 dyne/cm2.

Abstract: An integrated module of acoustic wave device with active thermal compensation comprises a substrate, an acoustic wave filter, an active adjustment circuit and at least one variable capacitance device. The acoustic wave filter comprises a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. Each of the variable capacitance device is connected in parallel to one of the series and shunt acoustic wave resonators. The active adjustment circuit outputs an active thermal compensation signal correlated to a thermal variation sensed by the thermal sensing acoustic wave resonator to the variable capacitance device. The active thermal compensation signal induces a capacitance variation of the variable capacitance device such that the impact of the thermal variation to the acoustic wave device is compensated.

Abstract: An acoustic wave filter having thermal sensing acoustic wave resonator comprises a substrate, a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. The thermal sensing acoustic wave resonator is one of a series acoustic wave resonator and a shunt acoustic wave resonator. Thereby the thermal sensing acoustic wave resonator plays dual roles of thermal sensing and acoustic wave filtering.

Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion, disposed on the substrate; a dielectric portion, disposed on the active circuit portion, wherein a hole is formed within the dielectric portion and the hole penetrates through the dielectric portion; and a radiating metal sheet, disposed on the dielectric portion; wherein the active circuit portion and the radiating metal sheet are coupled through the hole.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion including at least an active component and formed on a topside of the semiconductor device; and a radiating metal sheet formed on a backside of the semiconductor device. A hole is formed within the substrate and the hole penetrates through the substrate. The active circuit portion and the radiating metal sheet are coupled through the hole.

Abstract: A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.

Abstract: A method for aligning an inhomogeneous receiver with an anisotropic emitter on a wafer probing system, wherein a reference semiconductor die comprising a reference pad and an anisotropic emitter is formed on a semiconductor wafer, the reference pad is located at a reference-pad-and-anisotropic-emitter relative position corresponding to the anisotropic emitter, the method comprises following steps of: measuring a receiver center position of an inhomogeneous receiver configured on a wafer probing system by a profile sensor; measuring a reference tip position of a reference tip of a reference probe on a probe card by a measuring instrument; displacing the inhomogeneous receiver in an aligning displacement according to the reference-pad-and-anisotropic-emitter relative position, the reference tip position and the receiver center position; and aligning the reference tip with the reference pad by a probe-tip-and-pad aligning machine of the wafer probing system.

Abstract: A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.

Abstract: A method for fabricating bulk acoustic wave resonator with mass adjustment structure, comprising following steps of: forming a sacrificial structure mesa on a substrate; etching the sacrificial structure mesa such that any two adjacent parts have different heights, a top surface of a highest part of the sacrificial structure mesa is coincident with a mesa top extending plane; forming an insulating layer on the sacrificial structure mesa and the substrate; polishing the insulating layer to form a polished surface; forming a bulk acoustic wave resonance structure including a top electrode, a piezoelectric layer and a bottom electrode on the polished surface; etching the sacrificial structure mesa to form a cavity; the insulating layer between the polished surface and the mesa top extending plane forms a frequency tuning structure, the insulating layer between the mesa top extending plane and the cavity forms a mass adjustment structure.

Abstract: A method for forming cavity of bulk acoustic wave resonator comprising following steps of: forming a sacrificial epitaxial structure mesa on a compound semiconductor substrate; forming an insulating layer on the sacrificial epitaxial structure mesa and the compound semiconductor substrate; polishing the insulating layer by a chemical-mechanical planarization process to form a polished surface; forming a bulk acoustic wave resonance structure on the polished surface, which comprises following steps of: forming a bottom electrode layer on the polished surface; forming a piezoelectric layer on the bottom electrode layer; and forming a top electrode layer on the piezoelectric layer, wherein the bulk acoustic wave resonance structure is located above the sacrificial epitaxial structure mesa; and etching the sacrificial epitaxial structure mesa to form a cavity, wherein the cavity is located under the bulk acoustic wave resonance structure.

Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.

Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.

Abstract: A coaxial probe structure, comprising: a support member, comprising a first connecting member; a connector, comprising a second connecting member; a coaxial probe, connecting with a connecting end of the coaxial probe to a bottom of the connector, and extending downwards from the bottom of the connector to a probe tip, and an included angle formed at a junction of the probe tip and the connecting end; and an elastic body connecting the support member with the junction of the connecting end and the probe tip of the coaxial probe.

Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors; a plurality of second anchors; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.

Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.