Abstract: The present invention relates to analogue selectors, also known as analogue multiplexers, for audio equipment input source selection. The present invention provides an analogue input selector for selecting one of a number of analogue source devices. The selector comprises a plurality of input connections for coupling to the input sources, each said input connection being connected to a gain controller having at least zero and one or more non-zero gains, said input connection not including a semiconductor switch. Preferably the gain controllers are implemented using MOSFETs which are held at a voltage which is independent of the signal voltage.

Abstract: Audio transient suppression circuit (300) has two modes, a first, for example active mode in which the circuit operates to provide an audio signal output and a second, for example standby mode in which said audio signal output is suppressed. The circuit comprises at least one active signal processing stage having an output node (128), the output node having a dc signal path to a first dc voltage (104), said dc signal path including at least one first resistive element (122, 124). The circuit further comprises an output signal transient suppresser, said transient suppresser comprising a second resistive element (304) switchably connected (302) between a second dc voltage (102) and said output node. The second resistive element has a resistance selected such that when said second resistive element is connected the voltage on said output node in said second mode is substantially equal to a quiescent voltage on said output node in said first mode.

Abstract: A digital to analogue converter (DAC) system (30) is described which has a plurality of weighting elements (40) where some of the weighting elements have a different nominal weight from other elements. In a preferred arrangement pairs of elements with the same nominal weight are combined, with each pair of elements having more than two output states. A selection unit is coupled to the elements and an adder is coupled to the selection unit to sum the outputs of the weighted elements. In use, the DAC system receives a digital signal and the selection unit determines the output state of each element combination to provide values of the weighted elements which, when summed, are equivalent to the digital signal. The selection unit also determines the output state of each element in each element combination to minimise errors. An analogue to digital (A/D) converter (200) based on the DAC is also described.

Abstract: A switched capacitor digital-to-analogue converter (DAC) 400 for reducing signal dependent loading of a reference voltage source used by the converter comprises an active circuit (102) with a feedback element. The feedback element comprises a feedback capacitor (104), a second capacitor (106) and switches (402, 110) to connect the second capacitor to one of first and second reference sources to store charge on the second capacitor and to connect the second capacitor in parallel with the feedback capacitor to share said stored charge with the feedback capacitor. The switch is further configured to connect the second capacitor to a substantially signal-independent reference prior to connection of the second capacitor to said one of said first and second references. Connecting the second capacitor to a substantially signal-independent reference source prior to the selected first or second reference gives a linear signal-dependent loading of the first and second reference sources.

Abstract: A differential input, differential output transconductor for IC fabrication comprises a matched pair of field-effect transistors (10) whose source terminals (11) are connected together to a first fixed voltage, the substrate terminals are connected together to a second fixed voltage and the quiescent voltages of the gate terminals (12) are equal. The FETs are biassed in the triode region of operation for the expected gate-source voltage and signal voltages of equal but opposite polarity are superimposed on the gate terminals (12) of the FETs. Circuitry is disclosed to maintain the voltage of the drain terminals (13) and to transmit the differential - mode output current component at a higher impedance level to output circuitry. A common-mode bias stabilization circuit, a phase neutralizing circuit and active filter circuits are also disclosed.