Abstract: A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the f

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: A method of forming an oxide layer in an in-situ steam generation (ISSG) process, including providing a silicon substrate in a rapid thermal process (RTP) chamber and injecting a gas mixture into the RTP chamber. The method further includes heating a surface of the silicon substrate to a reaction temperature, so that the gas mixture reacts close to the surface to form steam and thereby oxidize the silicon substrate to form the oxide layer on the surface, and wherein the gas mixture comprises hydrogen (H2), oxygen (O2) and nitrous oxide (N2O).

Abstract: A method of forming gate sidewall spacers of two different widths, the method including providing a semiconductor substrate and providing a first and second gate structure on the semiconductor substrate. Each gate structure has at least one sidewall. The method includes blanket depositing, on said first and second gate structures, a first nitride layer and anisotropically etching the first nitride layer leaving at least some of said first nitride layer on at least one sidewall of each gate structure so as to form a first nitride sidewall spacer portion on each gate structure. The method further includes removing the first sidewall spacer portion from the first gate structure, blanket depositing, on said first and second gate structures, a second nitride layer, and anisotropically etching the second nitride layer leaving at least some of said second nitride layer on at least one sidewall of each gate structure so as to form a second nitride sidewall spacer portion on each gate structure.