Patents Assigned to Xambala Corporation
  • Patent number: 7710988
    Abstract: A structural matching engine for non-deterministic filtering operations is provided. The structural matching engine includes an active node processor (ANP) configured to process a state of an active list to determine possible future states of a non-deterministic finite automaton (NFA). The ANP processes the state according to rules. The structural matching engine includes an active list processor (ALP) configured to initiate a lookup for a token value corresponding to the state of the active list. The ALP provides a next sate of the active list to the ANP for processing according to the rules upon completion of the processing of the state by the ANP, wherein the possible future states of the NFA are linked by the ALP to form a target list, the target list stacked on top of the active list in a data structure. A processor and a method for filtering data associated with non-deterministic states are also included.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: May 4, 2010
    Assignee: Xambala Corporation
    Inventors: Devendra Tripathi, Keith Kong, Alak Deb, Debashis Chatterjee
  • Patent number: 7664938
    Abstract: A system including a CPU including logic for executing code from a location and at a time determined by an external entity, a data cache and a CPU management entity (CME) including logic for receiving data one unit at a time from an external data feeder. The data unit being arbitrarily defined mutually between the data feeder and the CME. The CME being coupled to the CPU. The CME including logic to provide the received data unit, a corresponding context information and a corresponding code address to the CPU, wherein the CPU includes logic for notifying the CME of a completed execution.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: February 16, 2010
    Assignee: Xambala Corporation
    Inventors: Devendra Tripathi, Sarin Chandran, Raman Muthukrishnan
  • Publication number: 20080068998
    Abstract: A switch including circuitry and methods for decreasing latency associated with initiating Internet communications are disclosed. The switch includes a host processor and a transport subsystem that receives incoming data and sends outgoing data. The switch also has a semantic processor. The semantic processor anticipates real-time communication by analyzing the incoming data for specific types of data from a first user in order to instruct the host processor to pre-fetch data needed to initiate real-time communications with a second user. The pre-fetching of the data needed to initiate real-time communications decreases the latency associated with establishing communications between the first user and the second user.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 20, 2008
    Applicant: XAMBALA CORPORATION
    Inventors: MOHIT JAGGI, Alak Deb