Abstract: A silicon carbide power diode device has a silicon carbide substrate on which a silicon carbide epitaxial layer with an active region is provided. A Schottky metal layer is on the active region, and a first electrode layer is on the Schottky metal layer. A first ohmic contact is on the silicon carbide substrate, and a second electrode layer is on the first ohmic contact. The active region of the silicon carbide epitaxial layer has a plurality of first P-type regions, a plurality of second P-type regions, and N-type regions. The first P-type regions and the second P-type regions lacking an ohmic contact are spaced apart with dimensions of the second P-type regions being minimized and the N-type regions being maximized for given dimensions of the first P-type region. Second ohmic contacts are located between the first P-type region and the Schottky metal layer.

Abstract: An epitaxial structure includes a composite base unit and an emitter unit. The composite base unit includes a first base layer and a second base layer formed on the first base layer. The first base layer is made of a material of InxGa(1-x)As(1-y)Ny, in which 0<x?0.2, and 0?y?0.035, and when y is not 0, x=3y. The second base layer is made of a material InmGa(1-m)As, in which 0.03?m?0.2. The emitter unit is formed on the second base layer 12 opposite to the first base layer 11, and is made of an indium gallium phosphide-based material. A transistor including the epitaxial structure is also disclosed.

Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Abstract: A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including gold on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.

Abstract: A cascode transistor device includes a semiconductor substrate, and a first and a second compound semiconductor transistors. The first compound semiconductor transistor includes a first n-type doping layer, a first p-type doping layer and a second n-type doping layer sequentially disposed on the semiconductor substrate. The second compound semiconductor transistor includes a third n-type doping layer, a second p-type doping layer and a fourth n-type doping layer sequentially disposed on the second n-type doping layer. Each of these doping layers is formed with an exposed metal contact. The exposed metal contact on the second n-type doping layer is electrically connected to the exposed metal contact on the third n-type doping layer.

Abstract: A microwave transistor has a patterned region between a source and a drain on a barrier layer. Within the patterned region, the surface of the barrier layer partially recessed downwards in the thickness direction to form a plurality of grooves. A gate covers the patterned region. The length of the gate is greater than the lengths of the grooves in the length direction of the gate, so as to completely cover the grooves. In one aspect, by arranging the grooves, the gate control capability of a component is improved and the short-channel effect is suppressed; in another aspect, an original heterostructure below the gate is preserved; in this way, the reduction of the conductive capability due to the reduction of the two-dimensional electron gas density is avoided; and accordingly the current output capability of the component is ensured while the short-channel effect is suppressed.

Abstract: A vertical-cavity surface-emitting laser (VCSEL) device includes a substrate, first and second-type doped distributed Bragg reflectors, first and second electrodes, an active layer, a surface relief layer having a surface relief indentation of a diameter (d4) ranging from 1.0-6.0 um, and a confinement member defining an aperture with a diameter (d2) ranging from 3.0-15 ?m. The second electrode is a ring-shaped p-contact metal having an inner diameter (d3) ranging from 8-17 ?m. The VCSEL device has a mesa structure that has a bottom mesa diameter (d1) ranging from 16-28 ?m. The diameters satisfy the relation of d1>d2>d3>d4. The surface relief layer has a thickness equaling to n/4 times a wavelength of a laser beam generated by the active layer with n being positive even numbers.

Abstract: A microwave transistor has a patterned region between a source and a drain on a barrier layer. Within the patterned region, the surface of the barrier layer partially recessed downwards in the thickness direction to form a plurality of grooves. A gate covers the patterned region. The length of the gate is greater than the lengths of the grooves in the length direction of the gate, so as to completely cover the grooves. In one aspect, by arranging the grooves, the gate control capability of a component is improved and the short-channel effect is suppressed; in another aspect, an original heterostructure below the gate is preserved; in this way, the reduction of the conductive capability due to the reduction of the two-dimensional electron gas density is avoided; and accordingly the current output capability of the component is ensured while the short-channel effect is suppressed.

Abstract: A Silicon Carbide (SiC) power device employing a heterojunction terminal includes: a cathode electrode, a substrate layer, an N-type SiC extension layer, an anode electrode, and a plurality of P-type structures disposed at interval. The plurality of P-type structures grow and form, via a heterogeneous epitaxy, using a P-type semiconductor material having a growth temperature less than that of SiC, and on the N-type SiC extension layer, and are evenly or unevenly distributed at periphery of the anode electrode, so as to form a heterogeneous terminal. Therefore, the embodiment effectively prevents impact on a doping characteristic of the N-type SiC extension layer, and can obtain a SiC device having a high breakdown voltage and low device turn-on voltage. Also provided is a manufacturing method of the SiC power device. The embodiment reduces requirements for a high-temperature or complex technique, provides a simple process, and reduces manufacturing costs.

Abstract: A vertical cavity surface emitting laser device includes a substrate, a first-type doped distributed Bragg reflector (DBR) disposed on the substrate, a first electrode disposed on the substrate, an active layer disposed on the first-type doped DBR, a second-type DBR disposed on the active layer, and a second electrode disposed on the second-type DBR. The second-type DBR defines a first doping concentration region, and a second doping concentration region disposed between the first doping concentration region and the active layer and that has a doping concentration less than that of the first doping concentration region. The second-type doped DBR has a confinement member formed in the first doping concentration region, and defining an aperture.