Abstract: A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.

Abstract: The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.

Abstract: A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.

Abstract: A method of generating a computer program, the method comprising: independently compiling a plurality of source code modules to generate a plurality of respective object modules comprising a plurality of respective threads explicitly designated by a user to be executed in parallel; in each of the object modules, inserting at least one symbol indicative of a property of the object module's thread potentially conflicting with a corresponding property of a thread of another of said object module as a result of parallel execution of those threads; executing a linker to perform a linking process on said object modules, the linking process comprising: assessing the symbols in conjunction with one another to determine whether a conflict exists between the threads of two or more of the respective object modules; and linking the object modules to generate a computer program in which said threads are executable in parallel, wherein the linking is performed in dependence on said assessment.

Abstract: A method comprising: independently compiling a plurality of modules of source code to generate a plurality of respective object modules comprising a plurality of respective parallel threads explicitly designated by a user to be executed in parallel on a target platform; in each of the object modules, inserting at least one symbol indicative of a usage of a resource of the target platform associated with the respective thread; executing a linker to perform a linking process for linking the object modules, wherein the linking process comprises assessing the symbols in conjunction with one another, and based on the assessment generating an indication relating to a usage of the resource required for execution of the threads in parallel.

Abstract: The invention relates to a device comprising a processor, the processor comprising: an execution unit for executing multiple threads, each thread comprising a sequence of instructions; and a plurality of sets of thread registers, each set arranged to store information relating to a respective one of the plurality of threads. The processor also comprises circuitry for establishing channels between thread register sets, the circuitry comprising a plurality of channel terminals and being operable to establish a channel between one of the thread register sets and another thread register set via one of the channel terminals and another channel terminal. Each channel terminal comprises at least one buffer operable to buffer data transferred over a thus established channel and a channel terminal identifier register operable to store an identifier of the other channel terminal via which that channel is established.

Abstract: Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.

Abstract: The invention provides a method of transmitting one or more tokens over a link between processors, whereby configurations of logical transitions on the lines are used to signal respective codes. The method comprises: transmitting a token by signalling a sequence of codes selected from said codes on the lines; and transmitting one or more additional codes on the lines to ensure that the total number of logical transitions on each line returns the link to a quiescent state following the signalling of said one or more tokens and additional codes.

Abstract: Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.

Abstract: A method comprising: independently compiling a plurality of modules of source code to generate a plurality of respective object modules comprising a plurality of respective parallel threads explicitly designated by a user to be executed in parallel on a target platform; in each of the object modules, inserting at least one symbol indicative of a usage of a resource of the target platform associated with the respective thread; executing a linker to perform a linking process for linking the object modules, wherein the linking process comprises assessing the symbols in conjunction with one another, and based on the assessment generating an indication relating to a usage of the resource required for execution of the threads in parallel.

Abstract: One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter value during execution. The execution unit comprises logic configured to identify an opcode representing a trap-if-late instruction in said sequence, and in response to execute the trap-if-late instruction by comparing a target value to the counter value and generating an exception on condition that the counter value represents a time that is late relative to said target value. Another aspect provides a compiler for inserting trap-if-late instructions based on timing constraints in higher-level code.

Abstract: A method of generating a computer program, the method comprising: independently compiling a plurality of source code modules to generate a plurality of respective object modules comprising a plurality of respective threads explicitly designated by a user to be executed in parallel; in each of the object modules, inserting at least one symbol indicative of a property of the object module's thread potentially conflicting with a corresponding property of a thread of another of said object module as a result of parallel execution of those threads; executing a linker to perform a linking process on said object modules, the linking process comprising: assessing the symbols in conjunction with one another to determine whether a conflict exists between the threads of two or more of the respective object modules; and linking the object modules to generate a computer program in which said threads are executable in parallel, wherein the linking is performed in dependence on said assessment.

Abstract: An integrated circuit and corresponding method of manufacture. The integrated circuit has a die comprising: an outer strengthening ring around a periphery of the die, the outer ring having one or more gaps; and an inner strengthening ring within the outer ring and around interior circuitry of the die, the inner ring having one or more gaps offset from the gaps of the outer ring. One or more conducting members are electrically isolated from said rings and electrically connected to the interior circuitry, each member passing through a gap of the inner ring and through a gap of the outer ring.

Abstract: The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is operable to determine three four-bit operand elements from the remaining eleven bits of the input, the three operand elements each having one of twelve possible binary values. The operand decoding logic is operable to decode an encoded group of the eleven bits to determine a first part of each of the three operand elements, and to read verbatim a verbatim group of the eleven bits to determine a second part of each of the three operand elements.

Abstract: A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal.

Abstract: A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.

Abstract: The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.