Abstract: A system comprising: a radar sensor configured to produce a set of radar readings distributed amongst a plurality of distance bins; an image projection module configured to project at least some of the radar readings onto an image comprising a 2D Cartesian grid of pixels based on the respective azimuth angles and elevations, wherein for each pixel where a radar reading is present the pixel comprises a respective value of at least one non-binary channel comprising at least one of measured property of the radar reading; and a machine learning model for image recognition, arranged to receive the image and to detect an object therein, wherein the machine learning model is configured to perform the detection based on at the values of the at least one non-binary channel for each pixel.

Abstract: A processing unit for generating an output vector is provided. The processing unit comprises an output vector register and a vector unit and is configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processing unit. The instruction set includes a vector processing instruction defined by a corresponding opcode, which causes the processing unit to: i) process, using the vector unit, at least two input vectors to generate a result value; ii) perform a rotation operation on the plurality of elements of the output register in which the result value or a value based on the result value is placed in the first end element of the output register.

Abstract: A method, apparatus, and system for detecting presence of an object of low radar cross section RCS (250) in an environment (200) are provided. Radar detection at one or more radar frequencies greater than 2 GHz is used to determine a steady state response profile (300) of the environment (200). The steady state response profile (300) comprises at least one indication of one or more reflected signals (202) from an object of high RCS in the environment (200). Radar detection at the one or more radar frequencies is then used to determine a test response profile (600) of the environment (200). The test response profile (600) is compared with the steady state response profile (300) to determine a presence of a, object of low RCS (250) in the environment by identifying at least partial absence of at least one of the reflected signals (202) in the test response profile (600).

Abstract: A processor comprising a register file comprising a bias register for holding a bias and a plurality of operand registers each for holding a respective number which together with the bias represents a respective value in a logarithmic number system; and an execution unit configured to, in response to receiving a logarithmic addition opcode: retrieve first and second numbers from first and second sources respectively; subtract the first number from the second number to determine a difference; and if the determined difference is less than or equal to a predetermined number, retrieve, from a look-up table, a third number mapped to the determined difference, and add the third number to the first number to determine a result; if the determined difference is greater than the predetermined number, determine the result to be the greatest of the first and second numbers; and store the result.

Abstract: A system comprising a data memory, a first processor with first execution pipeline, and a co-processor with second execution pipeline branching from the first pipeline via an inter-processor interface. The first pipeline can decode instructions from an instruction set comprising first and second instruction subsets. The first subset comprises a load instruction which loads data from the memory into a register file, and a compute instruction of a first type which performs a compute operation on such loaded data. The second subset includes a compute instruction of a second type which does not require a separate load instruction to first load data from memory into a register file, but instead reads data from the memory directly and performs a compute operation on that data, this reading being performed in a pipeline stage of the second pipeline that is aligned with the memory access stage of the first pipeline.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: A controller and method of classifying a user into one of a plurality of user classes. One or more voice samples are received from the user, from which a frequency spectrum is generated. One or more values defining respective features of the frequency spectrum are extracted from the frequency spectrum. Each of the respective features are defined by values of frequency, amplitude, and/or position in the spectrum. One or more of the respective features are resonant frequencies in the voice of the user. A user profile of the user is generated and comprises the extracted one or more values. The user profile is supplied to a machine learning algorithm that is trained to classify users as belonging to one of the plurality of user classes based on the one or more values in their respective user profile.

Abstract: A system comprising a data memory, a first processor with first execution pipeline, and a co-processor with second execution pipeline branching from the first pipeline via an inter-processor interface. The first pipeline can decode instructions from an instruction set comprising first and second instruction subsets. The first subset comprises a load instruction which loads data from the memory into a register file, and a compute instruction of a first type which performs a compute operation on such loaded data. The second subset includes a compute instruction of a second type which does not require a separate load instruction to first load data from memory into a register file, but instead reads data from the memory directly and performs a compute operation on that data, this reading being performed in a pipeline stage of the second pipeline that is aligned with the memory access stage of the first pipeline.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: A method of using a directional microphone unit having an array of constituent microphones. Each of a plurality of the microphones receives substantially white noise via a direct path from a source, and also receives an echo comprising a reflection of the white noise from at least one surface, thereby obtaining a received noise signal comprising a combination of the directly-received noise and the echo. For each of the plurality of microphones, a spacing is identified between lobes and/or troughs in a respective spectrum of the received noise signal as received by the respective microphone, thereby determining an additional distance travelled by the echo to the respective microphone relative to the direct path. A direction of the source is calculated based on the additional distance travelled for each of said plurality of microphones.

Abstract: A method of using a directional microphone unit having an array of constituent microphones. Each of a plurality of the microphones receives substantially white noise via a direct path from a source, and also receives an echo comprising a reflection of the white noise from at least one surface, thereby obtaining a received noise signal comprising a combination of the directly-received noise and the echo. For each of the plurality of microphones, a spacing is identified between lobes and/or troughs in a respective spectrum of the received noise signal as received by the respective microphone, thereby determining an additional distance travelled by the echo to the respective microphone relative to the direct path. A direction of the source is calculated based on the additional distance travelled for each of said plurality of microphones.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group.

Abstract: The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle activity from at least one specified source. The processor also comprises a thread scheduler for scheduling a plurality of threads to be executed by the execution unit, said scheduling being based on the respective activity handled by the threads; and a plurality of sets of registers connected to the execution unit. Each set of registers is arranged to store information representing a respective one of the plurality of threads, at least a part of the information being accessible by the execution unit for use in executing the respective thread when scheduled.

Abstract: A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.

Abstract: A method and corresponding tool for estimating program execution time. A higher-level structure is received as an input, representing control flow through an executable program. The higher-level structure comprises one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes. The levels of the higher-level structure are probed to extract a substructure representing a route through the program from a start instruction to an end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes. An execution time for the route through the program is estimated based on the extracted substructure, and a modification affecting the execution time is made in dependence on the estimation.

Abstract: A system comprising: a server; a computer terminal coupled remotely to the server via a network and installed with a web browser; and an external test platform, connected externally to the computer terminal, the test platform comprising a programmable target device and interface circuitry operable to communicate between the computer terminal and the target device. The server hosts a development tool available for download to the web browser via the network. The development tool comprises: one or more applets to be run by the web browser, and one or more web pages for display by the web browser to provide a user-interface for the development tool including to provide access to the one or more applets. The one or more applets at least comprise code-analysis applet software programmed so as when run by the web browser to operate said interface circuitry to: load code to be tested from the computer terminal onto the target device for test operation.

Abstract: The invention provides a method of transmitting messages over an interconnect between processors, each message comprising a header token specifying a destination processor and at least one of a data token and a control token. The method comprises: executing a first instruction on a first one of the processors to generate a data token comprising a byte of data and at least one additional bit to identify that token as a data token, and outputting the data token from the first processor onto the interconnect as part of one of the messages. The method also comprises executing a second instruction on said first processor to generate a control token comprising a byte of control information and at least one additional bit to identify that token as a control token, and outputting the control token from the first processor onto the interconnect as part of one of the messages.

Abstract: The invention provides a processor comprising a first port operable to generate a first indication dependent on a first activity at the first port, and a second port operable to generate a second indication dependent on a second activity at the second port. The processor also comprises an execution unit arranged to execute multiple threads; and a thread scheduler connected to receive the indications and arranged to schedule the multiple threads for execution by the execution unit based on those indications. The scheduling includes suspending the execution of a thread until receipt of the respective ready signal. The first activity and the second activity are each associated with respective corresponding threads.

Abstract: The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions including at least: a thread event enable instruction which sets a status to event-enabled to allow a thread to accept events, a wait instruction which sets the status to suspended pending at least one event upon which continued execution of the thread depends, and a thread event disable instruction which sets the status to event-disabled to stop the thread from accepting events. The continued execution comprises retrieval of a continuation point vector for the thread.