Abstract: A fast reset degaussing system includes a full wave rectifier bridge having a degaussing coil coupled in series therewith to a source of operating AC power. A variable current element is provided by a field effect transistor which produces a variable load upon the full wave rectifier bridge. An RC charging circuit is coupled to the control electrode of the field effect transistor to cause an exponentially decaying current within the transistor and thereby impose an exponentially load upon the full wave rectifier bridge. The degaussing coil current responds directly to the load imposed upon the rectifier bridge by the field effect transistor and produces an exponentially decaying alternating current suitable for cathode ray tube degaussing.

Abstract: A data compression system responsive to a preprocessed digitally encoded high definition video signal includes a discrete cosine transform, a frequency weighting filter, and an inverse discrete cosine transform circuit to provide a digitally encoded video signal within which the high frequency terms of the discrete cosine transform have been reduced. A motion compensated predictive coding data compression system organizes the current frame and a previous frame into a plurality of pixel blocks. The pixel blocks are compared by an error calculating and matching circuit under the influence of a timing control to provide an error value output. A spatial weighting factor is applied to each error value output to provide spatially weighted error values which are used to produce a corresponding plurality of motion vectors. The motion vector corresponding to the lowest weighted error value is selected by a motion vector selector for application to a channel buffer/encoder and eventual transmission.

Abstract: A video signal peak compressor circuit includes an emitter follower stage together with a feedback amplifier having a conduction threshold determined by a pair of voltage divider resistors. The feedback amplifier responds to increased conduction of the emitter follower stage to apply a compensating current to the emitter follower base and thereby impose a nonlinear compressing characteristic upon the emitter follower transfer function. In the embodiment shown, the emitter follower stage includes a PNP transistor having an input signal applied to its base and an output signal taken at its emitter which is coupled to operating supply by a pair of resistors. The feedback amplifier includes a PNP transistor having its emitter coupled to the junction point of a voltage divider, its base coupled to the junction of the emitter follower resistors and its collector coupled to the base of the PNP emitter follower stage.

Abstract: A slice circuit for a data signal includes a clamp for clamping the data signal and a comparator having a first input coupled to the clamp, a second input coupled to a filter and an output coupled to a D/A converter. The output of the D/A converter is coupled to the filter such that a pulse width modulated signal is developed in the comparator output which is converted to a DC voltage by the D/A converter and filter for controlling the data slice level. The pulse width modulated signal is the sliced data.

Abstract: A video white compression and peaking arrangement comprises a plurality of inverting amplifier transistors each tied to a common threshold level. RGB input video signals are applied to the inverting amplifier transistors which are ineffective for signals below the threshold level. The transistors are progressively turned on for input signals that exceed the threshold level resulting in non-linear negative feedback signals that compress the output signals by subtraction. A tuned circuit is coupled across the input of each inverting amplifier transistor for bypassing selected frequencies from the negative feedback effect and relatively peaking those frequencies in the output signal.

Abstract: A system for minimizing co-channel interference into NTSC receivers from digitally transmitted ATV signals. The NTSC receiver subjective random noise sensitivity characteristic is utilized to shape the ATV transmitter power curve. A complementary filter incorporated in ATV receivers for compensating for the shaped ATV transmitter power curve. The shaped ATV power curve emphasizes signals at the frequencies where the NTSC subjective random noise sensitivity is low and deemphasizes signals at the frequencies where the NTSC subjective sensitivity is high.

Abstract: A brightness management arrangement for equalizing the aging of the phosphor screen of a 16:9 aspect ratio cathode ray tube used for 4:3 aspect ratio video displays provides low level illumination of the unused portions of the phosphor screen when displaying 4:3 aspect ratio video. The unused end panels are divided into three sections with the illumination level of each section being determined by the illumination levels of adjacent areas of the 4:3 video display.

Abstract: A high definition television transmitting system includes a source of high definition analog RGB video signals which are converted to corresponding digitally encoded signals and thereafter compressed by a video encoder to a six megahertz bandwidth. The compressed data is formatted by a transmitter and processed in accordance with a Reed-Solomon error control system for broadcast as an NTSC-type broadcast signal. A high definition television receiver includes a high definition signal receiver coupled to the transmitter by a transmission link. The receiver extracts the compressed video, audio and ancillary data signals and applies a Reed-Solomon error correction thereto. The compressed video data is reconstructed by a video decoder and processed for high definition display.

Abstract: A frame of compressed video data is formatted for transmission into a plurality of data segments, a first group of which are encoded in the form of a plurality of four-level symbols and a second group of which are encoded in the form of a plurality of two-level symbols for providing improved noise performance. The partition between the first and second groups of data segments may be established on a fixed basis, a variable basis dependent upon the effective level of compression, or a combination of both. Preferably, the levels are selected such that the average levels of the transmitted M and N-level symbols are substantially equal to a non-zero value to assist lock-up of the receiver PLL and reduce transmission power.

Abstract: A dual HDTV/NTSC receiver includes a microprocessor for controlling a tuner for synthesizing the carrier frequencies of HDTV signals and NTSC signals. The HDTV signals are inherently of much lower power than the NTSC signals. The tuner initially synthesizes the carrier frequency of a desired HDTV signal which is attempted to be detected in an narrow band synchronous detector. Detection of the HDTV signal produces a high lock detect signal which causes the microprocessor to enable an HDTV processing channel. If no HDTV signal is detected, the lock detect signal remains low and the microprocessor controls the tuner for synthesizing the carrier frequency of the NTSC co-channel television signal. A high lock detect signal from the narrow band synchronous detector, indicating detection of the NTSC co-channel causes the microprocessor to enable the NTSC processing channel. A system for automatically programming the receiver and memorizing which type signal is present on each television channel is also shown.

Abstract: An oscillator control system includes a phase-locked loop having a programmable frequency divider operative within the loop. A switch is further included within the phase-locked loop to permit the loop to be open or closed in response to an input signal. A counter accumulates oscillator clock signal counts between each successive rising edge portion of the applied sync signal. A pair of shift registers sequentially store successive clock signal counts for the current and previous sync signal intervals. The output counts are compared for consistency by producing a difference signal therebetween which is utilized to control the phase-locked loop switch and close it once the consistency of sync signal has been established. The output counts of the shift registers are combined and used to provide a scaling factor which sets the frequency division of the programmable frequency divider within the phase-locked loop and properly scales the oscillator frequency to the sync signal frequency.

Abstract: A method and a circuit arrangement for two-line comb filtering a sampled and digitized composite color signal are disclosed wherein, depending on the similarity status determined by means of a display area (27) via a local and temporal gradient analysis, the respective type of luma/chroma separation, namely two-line combing, combing up, combing down, or simple decoding, and the respective proportion of combing and simple decoding in the luma and chroma output signals (LO-21, CO-21) are determined for each pixel.

Abstract: A flyback type power supply has a nominal 12 volt secondary winding that is connected to a rectifier through the primary winding of a saturable transformer. The secondary winding of the saturable transformer is connected in series with the DC load current supplied by the rectifier. A filter capacitor completes the circuit. Under no load conditions, the impedance presented by the primary of the saturable transformer is high and the output voltage developed across the filter capacitor is maintained at about 12.25 volts. Under full load conditions, the impedance presented is negligible.