Abstract: A bipolar transistor with a specific area resistance less than about 500 mOhms·mm2 comprises a first semiconductor region of a first conductivity type defining a collector region (2). A second semiconductor region of a second conductivity type defines a base region (3). A third semiconductor region of the first conductivity type defines an emitter region (4). A metal layer provides contacts (6, 7) to said base (3) and emitter regions (4). The metal layer has thickness greater than about 3 ?m.

Abstract: A temperature dependent switching circuit comprises a first transistor with a threshold voltage Vth having a negative temperature coefficient. A diode having a forward voltage drop with a negative temperature coefficient coupled with its anode connected to the drain of the first transistor and its cathode connected to the gate of the first transistor. A first resistor is coupled between a power supply terminal and the drain of the first transistor. A low voltage supply is terminal connected to the source of the first transistor. A second resistor is coupled between the gate of the first transistor and the low voltage supply terminal. A switching transistor has its source connected to the low voltage supply terminal and its gate coupled to the drain of the first transistor. The drain of the first transistor provides a voltage with a negative temperature coefficient equal to the sum of the forward voltage drop across the diode and the threshold voltage of the first transistor.

Abstract: A temperature independent low voltage reference circuit comprises a first transistor with a threshold voltage Vth having a negative temperature coefficient. A diode having a forward voltage drop with a negative temperature coefficient coupled with its anode connected to the drain of the first transistor and its cathode connected to the gate of the first transistor. A first resistor coupled between a power supply terminal and the drain of the first transistor. A low voltage supply terminal connected to the source of the first transistor. A second resistor coupled between the gate of the first transistor and the low voltage supply terminal. The drain of the first transistor provides a voltage with a negative temperature coefficient equal to the sum of the forward voltage drop across the diode and the threshold voltage of the first transistor.

Abstract: A switching circuit (20) comprising first and second switch terminals (2,3) and a switch (21). The switch (21) comprises a first bipolar transistor (22), having a collector connected to the first switch terminal (2) and an emitter connected to the second switch terminal (3), and a second bipolar transistor (23), having an emitter connected to the first switch terminal (2) and a collector connected to the second switch terminal (3). The switch (21) can be turned on by supply of a control current to the base of either the first or the second bipolar transistor.

Abstract: A bipolar transistor with a specific area resistance less than about 500 mOhms·mm2 comprises a first semiconductor region of a first conductivity type defining a collector region (2). A second semiconductor region of a second conductivity type defines a base region (3). A third semiconductor region of the first conductivity type defines an emitter region (4). A metal layer provides contacts (6, 7) to said base (3) and emitter regions (4). The metal layer has thickness greater than about 3 ?m.

Abstract: A high side switching circuit, comprising: a switching transistor; a charge pump drive circuit including a circuit for generating an oscillating signal; and a charge pump arranged to provide a gate drive voltage to the switching transistor in response to a control signal; wherein the charge pump is driven by the charge pump drive circuit, and the circuit for generating an oscillating signal comprises: an oscillator having a power supply input and first and second outputs, outputting first and second pulse trains respectively of the same frequency but out of phase such that when the first pulse train is high, the second pulse train is low and when the second pulse train is high, the first pulse train is low; first and second transistors connected in series with the drain of the first transistor connected to a high voltage input relative to the high level of the first and second pulse train pulses, the source of the first transistor connected to the drain of the second transistor, the source of the second trans

Abstract: A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).

Abstract: A method for implanting ions into a surface of a semiconductor structure covered by a layer of insulating material, for example into a trench wall covered by a layer of oxide. A beam of ions is directed at a glancing angle to the layer of insulating material such that a substantial proportion of ions which are implanted into the semiconductor structure surface are scattered from the beam by the layer of insulating material. It is possible therefore to implant ions into a trench wall without requiring a beam source arranged to deliver a beam at a large angle to the trench wall surface.

Abstract: A current-limit circuit comprising a control transistor coupled to a power transistor in a current mirror configuration. A switch transistor is operatively coupled between the output of the power transistor and the control transistor to selectively activate the control transistor in response to an over current condition detected by a defect transistor. Current drawn through the power transistor in the over current condition is limited by the control transistor which is powered from the gate of the power transistor. The power and detect transistors are integrated on a semi-conductor substrate of a first conductivity type defining first and second surfaces. An array of adjacent transistor body regions of a second conductivity type provided adjacent said first surface with gate electrodes extending between adjacent body regions and insulated therefrom by a gate insulator layer. Transistor source regions of said first conductivity type are provided in said body regions adjacent said gate electrodes.

Abstract: A power FET device includes a semiconductor wafer substrate having first and second surfaces, a gate electrode extending over the first surface of the substrate but insulated therefrom, and a drain electrode extending over the second surface of the substrate. The gate electrode defines a regular array of apertures. An FET body region of a first conductivity type is formed in the first surface of the substrate beneath each gate electrode aperture, each body region extending laterally from edges of the gate electrode defining the aperture. An FET source region of a second conductivity type is formed within the body region beneath each gate electrode aperture, each FET source region extending from the edges of the gate electrode a second distance less than the first distance. An FET channel region extends around the periphery of each source region. Pairs of adjacent gate electrode apertures define there between a strip of gate electrode the width of which varies along the length of the strip.

Abstract: A method for reducing damage to a semiconductor structure resulting from migration of constituents of a first component part (3) of the structure into a subsequently deposited second component part (8) of the structure which makes contact with a surface of the first component part (3). A third component part (10) of the structure is deposited before the second component part (8), the third component part (10) being positioned so as to be contacted by the second component part (8) adjacent the said surface of the first component part (3). The third component part (10) has a composition such that it acts as a donor of constituents (12) to the second component part. The donor constituents (12) migrate into the second component part (8) when the second component part (8) is deposited and reduce the migration of constituents (11) of the first component part (3) into the second component part (8). If the first component part (3) is silicon, the third component part (10) may be polysilicon.

Abstract: A current-limit circuit comprising a control transistor coupled to a power transistor in a current mirror configuration. A switch transistor is operatively coupled between the output of the power transistor and the control transistor to selectively activate the control transistor in response to an over current condition detected by a defect transistor. Current drawn through the power transistor in the over current condition is limited by the control transistor which is powered from the gate of the power transistor. The power and detect transistors are integrated on a semi-conductor substrate of a first conductivity type defining first and second surfaces. An array of adjacent transistor body regions of a second conductivity type provided adjacent said first surface with gate electrodes extending between adjacent body regions and insulated therefrom by a gate insulator layer. Transistor source regions of said first conductivity type are provided in said body regions adjacent said gate electrodes.

Abstract: A semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations extending into and through the body region such that lower side walls of each indentation are defined by portions of the body and drain regions and upper side walls of each indentation are defined by the source region. A lower portion of each indentation is filled with a gate region isolated from the side walls by a first insulating layer and covered by a second insulating layer. A source conductor overlies the upper surface and is electrically connected to the source regions, and a gate conductor is electrically connected to each gate region. The source conductor extends into all upper portion of each indentation to contact portions of the upper side Walls of the indentation which are defined by the source regions.

Abstract: A guard ring structure formed around the periphery of a bipolar semiconductor device. A guard region (11) is formed in a substrate (1) of the device so as to extend adjacent a peripheral portion of the device. An insulating layer (3) is formed on the substrate between the peripheral portion of the device and the guard region (11). A polysilicon layer (13) is formed on the insulating layer (3) and covered with a layer of densified dielectic (14). Electrical interconnections are provided between the polysilicon layer (13) and the guard region (11) at spaced apart portions of the device where the guard structure does not need to be protected by the densified dielectric.

Abstract: A method of semiconductor device fabrication comprising forming at least the indentation in a surface of a semiconductor body. The indentation is partially filled with a filler material such that walls of the indentation are exposed above an upper surface of the filler material. First and second dopants are introduced through the exposed walls of the indentation and first and second doped regions formed. The first doped region extends into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material. The second doped region extends into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material.

Abstract: An amplifier circuit comprises a first amplifier stage controlling a second gain stage which is coupled between a voltage input node and an output node. A frequency compensating circuit is coupled between a compensating circuit node of the gain stage and a control input of the gain stage. The gain stage comprises first and second output devices arranged such that for a given gate voltage, the output current from the first device is greater than the output current from the second device. The output devices have a common source coupled to the input node and a common gate coupled to the first amplifier stage. The drain of the first output device is coupled to the output node and the drain of the second output device is coupled to the compensating circuit node with a resistance device connected between the two drains.

Abstract: A driver circuit for a discharge lamp. A voltage source delivers a variable voltage to a constant current source which is connected to the lamp. The delivered voltage is varied to stabilize the supply of power to the lamp. The delivered voltage may be controlled in response to variations in lamp voltage.

Abstract: A gated semiconductor device comprising a substrate defining an active surface area including source regions, and a series of gates formed adjacent and insulated from the source regions. A source electrode contacts the source regions. A termination extends around the periphery of the active surface area, The termination comprises a gate electrode and a layer of conductive material electrically connected between the gate electrode and the gates. The layer of conductive material extends to the source electrode and incorporates a series of regions which are alternately N and P type so as to define a series of breakdown diode junctions distributed around the active surface area and interposed between tie gate electrode and source electrode, In normal operation gate current flows through portions of the conductive layer which do not incorporate diode junctions. In the event that the gate/source voltage exceeds a predetermined level, the diode junctions break down, shorting the gate to the source.

Abstract: An electric circuit comprising a transformer having first and second magnetically coupled inductors, a first switch which is connected to the first inductor, a second switch which is connected to the second inductor so as to be turned on and off by the second inductor; and a timing circuit for connection to the first switch for turning the first switch on and off. The second inductor is magnetically coupled to the first inductor such that flux reversal in the first inductor which occurs as the first switch is turned off will induce flux reversal in the second inductor which will thereby turn on the second switch. The circuit includes a damping element arranged to damp the operation of the second switch.