Abstract: A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be performed when the RPT instruction is executed depends upon an initial instruction. If, for example, the initial instruction is an ADD, then the RPT instruction causes an ADC operation to be performed, thereby facilitating efficient coding of an extended precision addition operation. The locations of the operands for the RPT instruction are assumed to be in predetermined memory locations. When coding a repeated operation, rather than following the initial instruction with one or more instructions of the same form, the initial instruction is followed by one or more of the shorter RPT instructions, thereby conserving memory space and facilitating backward compatibility with an instruction set that does not have the RPT instruction.

Abstract: Linearity correction is performed by determining whether a data output value (DOUT) from an analog-to-digital converter (ADC) is in a first subrange or a second subrange. If DOUT is in the first subrange, then DOUT is scaled by a first scaling correction factor (SCF1), and the result is adjusted by a first best fit adjustment value (BFAV1). If DOUT is in the second subrange, then DOUT is scaled by a second scaling correction factor (SCF2), and the result is adjusted by a second best fit adjustment value (BFAV2). The data output range of an ADC can be processed in many ranges of such subranges. Techniques are set forth for determining SCF1, SCF2, BFAV1 and BFAV2. Employing the linearity correction method allows a low-cost microcontroller having an ADC to perform adequate linearity correction on the ADC output data without having to store an INL lookup table.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: A keypad encoding circuit contains a voltage dividing network and an integrated circuit. The voltage dividing network includes a string of resistors that generates an encoding signal voltage. The integrated circuit converts the encoding signal voltage into a digital value indicative of which of the keys has been pressed. The cost of the voltage dividing network is reduced by forming the resistors from a layer of conductive carbon and avoiding the cost of providing discrete resistors. Each resistor has the same resistance even where the dimensions of the conductive carbon patches that form the resistors vary. Providing the resistors does not involve additional manufacturing cost because the resistors are made in the same step as are the landing pads of the voltage dividing circuit. Manufacturing costs associated with etched printed circuit board layers are avoided because inexpensive printed layers are used to realize the required traces and resistors.

Abstract: An analog-to-digital converter (ADC) exhibiting an uncorrected non-linear transfer function receives measured analog voltage amplitudes and outputs uncorrected digital values. A calibration circuit receives each uncorrected digital value and outputs a corrected digital value. The measured analog voltage amplitudes received by the ADC and the corresponding corrected digital values output by the calibration circuit define points approximating an ideal linear transfer function of the ADC. The calibration circuit performs piecewise-linear approximation of the uncorrected transfer function and associates each uncorrected digital value with one of N linear segments that join at inflection points on the uncorrected transfer function. The inflection points are determined using the second derivative of the uncorrected transfer function. The calibration circuit calculates each corrected digital value using no more than 2N+2 stored calibration coefficients.

Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analog sensor signal is chopped by the chopper switches at a chopping frequency below the processor noise frequency. The ADC performs conversions a rate higher than the chopper frequency such that multiple first conversions are performed when the chopper switches are in a first configuration and multiple second conversions are performed when the chopper switches are in a second configuration. The first LPF attenuates the high frequency noise, converts the first conversions into first information, and converts the second conversions into second information. The inverter inverts the second information. The second LPF attenuates transposed 1/F noise and converts the first information and the inverted second information into ADC output values.

Abstract: A machine code API can be loaded onto an eight-bit, register-based virtual machine. A higher level script that is interpreted by a script interpreter of the virtual machine can then use the new functionality provided by the added API. The API may, for example, provide access to hardware of the underlying platform that is otherwise inaccessible to a higher level script. The API loading feature sees use where the virtual machine is remotely deployed in the field but can be communicated with via a bidirectional link. The API is communicated to the virtual machine via the bidirectional link and the API is loaded onto the virtual machine. The API is assigned a reference that a higher level script can use to call the API. Using this feature, various APIs can be loaded and their operations tested. Unwanted machine code APIs can also be erased from the virtual machine.

Abstract: A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory. The SDRAM-interface controller is configured to communicate with one or more SDRAMs. The SDRAM-interface controller provides a plurality of interface signals to the SDRAM via a dedicated port. One of the interface signals, an SDRAM address/control signal, has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.

Abstract: A programmable spread spectrum clock generator (SSCG) reduces electromagnetic interference by spreading the frequency bandwidth of an output signal. The rate at which the frequency of the output signal changes, as well as other aspects of the output signal, are software programmable. The programmable SSCG receives a periodic signal whose cycles have substantially identical periods and outputs the output signal whose cycles have periods that vary smoothly over a plurality of cycles of the periodic signal. The programmable SSCG generates a control signal using the periodic signal. The programmable SSCG includes a variable delay element that generates the output signal by delaying the periods of the periodic signal based on the magnitude of the control signal. The output signal is generated without using a phase locked loop. Moreover, successive cycles of the output signal rarely have identical periods.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: A high security microcontroller (such as in a point of sale terminal) includes tamper control circuitry for detecting vulnerability conditions: a write to program memory before the sensitive financial information has been erased, a tamper detect condition, the enabling of a debugger, a power-up condition, an illegal temperature condition, an illegal supply voltage condition, an oscillator fail condition, and a battery removal condition. If the tamper control circuitry detects a vulnerability condition, then the memory where the sensitive financial information could be stored is erased before boot loader operation or debugger operation can be enabled. Upon power-up if a valid image is detected in program memory, then the boot loader is not executed and secure memory is not erased but rather the image is executed. The tamper control circuitry is a hardware state machine that is outside control of user-loaded software and is outside control of the debugger.

Abstract: A script is stored on a remote control device. When a key is pressed, an interpreter on the remote control device interprets the script thereby causing codeset information (for example, key codes and protocol information) stored on the remote control device to be used to output a sequence of marks and spaces. Adjacent marks are combined into a larger mark and adjacent spaces are combined into a larger space. From these marks and spaces, a mark/space table and a string of timing information are generated. The mark/space table and the string of timing information are then used to generate an operational signal that is transmitted from the remote control device. In one embodiment, only one mark/space table and one string of timing information is ever present on the remote control device at one time. This reduces memory requirements, thereby reducing manufacturing cost of the remote control device.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor.

Abstract: A hardware debug device is usable to debug a target such as a microcontroller or microprocessor. A host instructs the hardware debug device what tests to perform on the target by sending a non-compiled script of text across a standardized script-based interface. The hardware debug device receives and interprets the script and sends appropriate microcommands to the on-chip debugger of the target to carry out actions specified by the script. The syntax of the interpreted script language is rich and allows scripts to define complex looping and testing actions. New scripts can be written to accommodate different target processors without changing the hardware debug device. Because complex testing operations are performed by the hardware debug device, network traffic at the host is reduced. The use of the interpreter and scripts also allows the cost of the hardware debug device to be reduced and reliability of the device to be increased.

Abstract: A remote control device detects that a command has been chosen. A command may, for example, have been chosen by a user pressing a key on the remote control device. In response, the remote control device generates a mark/space table and a string of timing information. The string of timing information includes entries that refer to mark time values and space time values in the mark/space table. The string of timing information also may contain special control portions (for example, a control portion can indicate that a portion of the string of timing information should be repeated a given number of times). The mark/space table and the string of timing information are then used to generate an operational signal that is transmitted from the remote control device. The mark/space table and string of timing information is a particularly compact way of describing an operational signal for a remote control device.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: An interactive, web-based codeset selection and development tool transmits hypertext documents from a web server to a web browser of a developer of microcontroller code for a new remote control device. The hypertext documents include selection criteria for groups of codesets stored in a central database of codesets. The developer selects the most appropriate codesets for the new remote control device using the selection criteria. The selection and development tool converts each of the selected codesets into a plurality of strings of timing information. The strings are encrypted and transmitted to the developer along with a signal engine. The developer loads the encrypted strings and the signal engine into a new microcontroller that has a factory-programmed decryption key. The microcontroller decrypts the encrypted strings of timing information and uses them and the signal engine to generate operational signals that control various functions of electronic consumer devices.

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.