Microsoft Patents

Microsoft Corporation develops, licenses, and supports a wide range of software products, services, and devices, including the Windows operating system, Microsoft Office application suite, Windows Phone operating system, Xbox game console platform, Windows Server, Windows SQL Server and Microsoft Azure cloud platform.

Microsoft Patents by Type

  • Publication number: 20170085521
    Abstract: A unified messaging system allows the receipt and sending of different messages across devices is established by creating relationships that leverage the capabilities of different devices. A message server establishes a relationship with a mobile device. Through the relationship, the message server can use the mobile device to send different types of messages that the server computer cannot transmit. A relationship between a client and a server extends this capability to the client. Through these relationships, a client can retrieve mobile device messages as well as generate them. The generated mobile device messages are transmitted to the message server. The message server determines that the received messages are mobile device messages that the server cannot deliver and sends the mobile device messages to the user's mobile device. The mobile device receives the mobile device messages from the message server and transmits the mobile device message to recipient mobile devices.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Samuel J. Neely, John Allen Atwood, Harvinder S. Bhela, Selvaraj Nalliah, David P. Limont, Katy Chen, Omar Aftab, Juan Vicente Esteve Balducci
  • Publication number: 20170086078
    Abstract: Techniques for wireless connectivity using white spaces (e.g., television (TV) white spaces) are described. In at least some embodiments, movement of a device operating as a white space access point is monitored by local sensors within the device. Movement data that is gathered by the local sensors is used to determine an upper bound of distance traveled. When the upper bound reaches a threshold distance, various actions can be performed relating to the data transmission, such as to cease transmission or to utilize different portions of the radio spectrum.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Amer Aref Hassan, Paul W. Garnett, Paul William Alexander Mitchell
  • Publication number: 20170085835
    Abstract: A user device within a communication architecture, the user device comprising: an image capture device configured to determine image data and intrinsic/extrinsic capture device data for the creation of a video channel defining a shared scene; a surface reconstruction entity configured to determine surface reconstruction data associated with the image data from the image capture device; a video channel configured to encode and packetize the image data and intrinsic/extrinsic capture device data; a surface reconstruction channel configured to encode and packetize the surface reconstruction data; a transmitter configured to transmit the video and surface reconstruction channel packets; and a bandwidth controller configured to control the bandwidth allocated to the video channel and the surface reconstruction channel.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Juri Reitel, Martin Ellis, Andrei Birjukov, ZhiCheng Miao, Ryan S. Menezes
  • Publication number: 20170083866
    Abstract: Techniques to manage remote events are described. An apparatus may comprise a processor circuit and a remote event application arranged for execution by the processor circuit. The remote event application may be operative to manage remote event notifications for a publisher entity and a subscriber entity. The remote event application may comprise, among other elements, an event monitor component operative to receive an external event notification message with a publisher entity event for the publisher entity. The event monitor component may select a custom event receiver component associated with the publisher entity from among multiple custom event receiver components, and send the external event notification message to the selected custom event receiver component. The custom event receiver component may implement custom business logic, such as code callouts designed for specific application programs or system programs. Other embodiments are described and claimed.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Roma Shah, Vijay Balaji M., Sharad Nandwani, Pradeep Kamalakumar, Atanu Banerjee, Ashish Kumar Singhal, Suresh Sunku
  • Publication number: 20170085386
    Abstract: When theft protection of a computing device is initiated, credentials of the user are provided to one or more services that verify the credentials and generate a recovery key. A data value is generated based on the recovery key and an identifier of the computing device (e.g., by applying a cryptographic hash function to the recovery key and the computing device identifier), and the data value is provided to the computing device, which stores the data value at the computing device. When a user is prompted to prove his or her ownership of the device, the owner can prove his or her ownership of the device in different manners by accessing the one or more services via a network (e.g., the Internet), or by providing the recovery key (e.g., obtained using another computing device) to the computing device.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Mihai Irinel Susan, Bogdan Andreiu, Scott R. Shell, Scott Michael Bragg, Ling Tony Chen
  • Publication number: 20170083875
    Abstract: Information management systems with time zone information, including event scheduling processes are disclosed. One aspect of the invention is directed toward a computer-implemented scheduling method that can include identifying a difference between a participant time zone and a user time zone, reviewing availability information for the participant and/or one or more selected time preference periods for the participant, and selecting a time range for an event. The method can further include reviewing one or more selected time preference periods for the user. Another aspect of the invention is directed toward a computer-implemented method for associating time zone information with a contact in an information management program application that includes selecting a contact, analyzing contact information associated with the contact, and determining a time zone for the contact based on the analysis of the contact information.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Colin Fitzpatrick, Jeff Eldridge, Mohamed Anas Abbar
  • Publication number: 20170083318
    Abstract: Apparatus and methods are disclosed for configuring, operating, and compiling code for, block-based processor architectures. In one example of the disclosed technology, a block-based processor includes processor cores configured to decode an instruction block header for a block-based processor instruction block including one or more fields and configure at least one of the cores to execute instructions in the instruction block according to a mode of operation specified by at least one of the fields, the modes including one or more of the following: core fusion operation, vector mode operation, memory dependence prediction operation, and/or deterministic order of execution.
    Type: Application
    Filed: December 23, 2015
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083806
    Abstract: The description relates to controllable device marking. One example can be manifest as a device that has a housing and a marking apparatus integrated into the housing. The marking apparatus can include a display and a disablement mechanism. While the disablement mechanism is in a first state the display is controllable to allow content presented on the display to be defined and when the disablement mechanism is transitioned to a second state the content is persisted and unchangeable on the display.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Vladimir HOLOSTOV, Austin CZARNECKI, Julia MEINERSHAGEN
  • Publication number: 20170083526
    Abstract: An intelligent tabular big data presentation in search environment based on prior human input configuration is provided. In some examples, a server may execute a search service that may receive a request from a party associated with the data to modify a presentation of a subset of the data and may present configuration options to the requesting party. The configuration options may include a selection of the subset of the data and parameters associated with the presentation of the subset of the data. The selected subset of the data may be formatted based on the received selection of the configuration options. A search query associated with the data may be received and may be executed on the subset of the data. A preview table may be generated and provided based on two dimensionally ranked search results of the subset of the data in accordance with the selection of the parameters.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Chun Ming Chin
  • Publication number: 20170083301
    Abstract: A high level programming language provides a nested communication operator that partitions a computational space. An indexable type with a rank and element type defines the computational space. The nested communication operator partitions a specified dimension of an index indexable type into segments specified by a segmentation vector and returns an output indexable type that represents the segments. By doing so, the nested communication operator allows data parallel algorithms to operate on the segments as individual units.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventor: Paul F. Ringseth
  • Publication number: 20170083314
    Abstract: Apparatus and methods are disclosed for initiating instruction block execution using a register access instruction (e.g., a register Read instruction). In some examples of the disclosed technology, a block-based computing system can include a plurality of processor cores configured to execute at least one instruction block. The at least one instruction block encodes a data-flow instruction set architecture (ISA). The ISA includes a first plurality of instructions and a second plurality of instructions. One or more of the first plurality of instructions specify at least a first target instruction without specifying a data source operand. One or more of the second plurality of instructions specify at least a second target instruction and a data source operand that specifies a register.
    Type: Application
    Filed: February 15, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083315
    Abstract: Systems, apparatuses, and methods related to a block-based processor core composition register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include one or more sharable resources and a programmable composition control register. The programmable composition control register can be used to configure which resources of the one or more sharable resources are shared with other processor cores of the plurality of processor cores.
    Type: Application
    Filed: December 23, 2015
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083316
    Abstract: Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.
    Type: Application
    Filed: February 15, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083119
    Abstract: A stylus pen is disclosed that can be used as an input device to a digitizer associated with a computer screen on a computing device, such as a computer, mobile device, tablet, etc. The stylus pen can include a voltage boost circuit that generates a stylus output signal on an antenna output. The voltage boost circuit has a charging portion and a discharging portion. Both portions have transistors that are activated and deactivated through pulsed control signals. However, a pulse duration for each control signal is separately controllable through different RC-based circuits. Additionally, the voltage boost circuit provides power savings by draining the output voltage signal to a positive voltage rail, rather than ground.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Michael Jensen, Justin Coppin
  • Publication number: 20170083321
    Abstract: Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using an instruction decoder that decodes instructions having variable numbers of target operands. In one example of the disclosed technology, a block-based processor core includes an instruction decoder configured to decode target operands for an instruction in an instruction block, the instruction being encoded to allow for a variable number of target operands and a control unit configured to send data for at least one of the decoded target operands for an operation performed by the at least one of the cores. In some examples, the instruction indicates target instructions with a vector encoding. In other examples, a variable length format allows for the indication of one or more targets.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083320
    Abstract: Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. Embodiments of the disclosed technology use read instructions to retrieve a value from a specified register in the register file of the processor architecture and send the value for use by one or more targets (e.g., other instructions in the instruction block). The read instruction may be predicated such that the instruction is only executed when a predicate condition is satisfied. In some examples of the disclosed technology, a compiler for such processors performs an analysis of the source and/or object code being compiled in order to determine whether operation(s) along conditional paths can be executed before or concurrently with determination of a condition on which the conditional operation(s) depend, thus improving processor efficiency.
    Type: Application
    Filed: January 22, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083324
    Abstract: Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.
    Type: Application
    Filed: October 23, 2015
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083322
    Abstract: Apparatus and methods are disclosed for decoding targets from an instruction and transmitting data to those targets in accordance with a current instruction. Multimodal target hardware is used in conjunction with one or more of the routers so as to route data to an appropriate target. The data can be one or more operands or a predicate and the targets can include operand buffers, broadcast channels, and general registers. In this way, operands, for example, can be directed for use with multiple subsequent instructions, and there are multiple modes for distributing the operands to the multiple instructions.
    Type: Application
    Filed: March 17, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083330
    Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.
    Type: Application
    Filed: March 3, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083325
    Abstract: Apparatus and methods are disclosed for dynamic nullification of memory access instructions, such as memory store instructions. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores. One of the cores can include an execution unit configured to execute memory access instructions comprising a plurality of memory load and/or memory store instructions contained in an instruction block. The core can also include a hardware structure storing data for at least one predicate instruction in the instruction block, the data identifying whether one or more of the memory store instructions will issue if a condition of the predicate instruction is satisfied. The core may further include a control unit configured to control issuing of the memory access instructions to the execution unit based at least in a part on the hardware structure data.
    Type: Application
    Filed: December 23, 2015
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083326
    Abstract: Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.
    Type: Application
    Filed: February 1, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083327
    Abstract: Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.
    Type: Application
    Filed: February 1, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083328
    Abstract: Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.
    Type: Application
    Filed: March 3, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083329
    Abstract: Apparatus and methods are disclosed for nullifying one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain a register identification of at least one of a plurality of registers, based on a target field of the nullification instruction. A write to the at least one register associated with the register identification is nullified. The nullification instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified write to the at least one register, a subsequent instruction is executed from a second, different instruction block.
    Type: Application
    Filed: March 3, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083319
    Abstract: Apparatus and methods are disclosed for generating and using block branch metadata in block-based processor architectures. In one example of the disclosed technology, a block-based processor is configured to dynamically generate metadata representing control flow, exit points, and control flow probabilities for an instruction block while decoding and executing the block. The metadata can be used with subsequent invocations of the instruction block for branch and memory dependence predictions. In some examples, an incomplete portion of a control flow representation is generated for a number of predicated instructions and stored in a memory or storage device for enhancing prediction and prefetch for subsequent invocations of an instruction block.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083211
    Abstract: Focused attention elements are provided as a mechanism to explicitly call a user's attention to a specific part of a communication or a document. The fact that a user was mentioned in a conversation or a collaborated document may be used as a signal the conversation or a document section is more relevant to them. If a user whose attention is drawn through a focused attention element is not among the recipient list of the communication or collaborator list for the document, they may be added automatically to the list. Selected portions of a conversation or document to which the attention of one or more users is drawn through the focused attention element may be emphasized, highlighted, or shown differently from a remainder of the conversation or document.
    Type: Application
    Filed: March 23, 2016
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: NITHYA RAMKUMAR, TOM LAIRD-MCCONNELL, SHAN QU, SANGYA SINGH
  • Publication number: 20170083337
    Abstract: Technology related to prefetching instruction blocks is disclosed. In one example of the disclosed technology, a processor comprises a block-based processor core for executing a program comprising a plurality of instruction blocks. The block-based processor core can include prefetch logic and a local buffer. The prefetch logic can be configured to receive a reference to a predicted instruction block and to determine a mapping of the predicted instruction block to one or more lines. The local buffer can be configured to selectively store portions of the predicted instruction block and to provide the stored portions of the predicted instruction block when control of the program passes along a predicted execution path to the predicted instruction block.
    Type: Application
    Filed: February 12, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventor: Douglas C. Burger
  • Publication number: 20170083334
    Abstract: Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the physical processor cores that share the sharable resource.
    Type: Application
    Filed: December 23, 2015
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083335
    Abstract: Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. In particular embodiments, a processor core in a block-based processor comprises: one or more functional units configured to perform functions using one or more operands; an instruction window comprising buffers configured to store individual instructions for execution by the processor core, the instruction window including one or more operand buffers for an individual instruction configured to store operand values; a control unit configured to execute the instructions in the instruction window and control operation of the one or more functional units; and a broadcast value store comprising a plurality of buffers dedicated to storing broadcast values, each buffer of the broadcast value store being associated with a respective broadcast channel from among a plurality of available broadcast channels.
    Type: Application
    Filed: March 18, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083331
    Abstract: Apparatus and methods are disclosed for performing memory operations instructions in a block-based processor architecture. In certain examples of the disclosed technology, a block-based processor core coupled to memory includes a control unit configured to issue one or more memory operations encoded in an instruction block allocated to the core and to commit the core when execution of the instruction block is complete, a memory store queue configured to cache one or more operands for the one or more memory operations, where a result of performing the memory operations is not architecturally visible unless the instruction block is committed by the control unit, and a memory interface configured to store the cached operands in the memory responsive to the instruction block committing. In some examples, the block-based processor core supports memory synchronization using load linked and store conditional instructions.
    Type: Application
    Filed: March 16, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083339
    Abstract: Technology related to prefetching data associated with predicated stores of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated store instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated store instruction and initiate a memory operation associated with the calculated target address before a predicate of the predicated store instruction is calculated.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083431
    Abstract: Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions. The block-based processor core includes execution control logic and core state access logic. The execution control logic can be configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode. The core state access logic can be configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core during the debug mode.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083338
    Abstract: Technology related to prefetching data associated with predicated loads of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated load instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated load instruction and issue a prefetch request to a memory hierarchy of the processor for data at the calculated target address.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083343
    Abstract: The disclosed technology can be used for executing and committing instruction blocks of a block-based processor architecture out-of-order. In one example of the disclosed technology, an apparatus can include a plurality of block-based processor cores which can include a first group of cores and a second group of cores. The first group of cores can be configured to commit instruction blocks of the set of instruction blocks in a sequential program order. The second group of cores can be configured to commit instruction blocks of the set of instruction blocks out-of-order relative to the sequential program order.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventor: Douglas C. Burger
  • Publication number: 20170083341
    Abstract: Systems and methods are disclosed for fetching and decoding instructions in block-based processor architectures. In one example of the disclosed technology, a block-based processor core can be used for executing an instruction block. The instruction block can include an instruction header and one or more instructions. The block-based processor core can include header decode logic and fetch logic that are in communication with each other. The header decode logic can be configured to decode the instruction block header to determine starting positions of a plurality of sub-blocks within the instruction block. The fetch logic can be configured to initiate parallel fetch and decode operations for the plurality of sub-blocks.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 23, 2017
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20170083340
    Abstract: Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.
    Type: Application
    Filed: March 3, 2016
    Publication date: March 23, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Patent number: 9599757
    Abstract: Tooling and optic elements for a retro-imaging system may be formed on order near atomic level of accuracy by making use of either etching or growth techniques of a cubic crystal lattice, such as silicon. The elements may be formed directly using selective etching or epitaxial growth by coating and clear resin lamination, or replicated to avoid shrinkage and curvature by use of low shrinkage resins or double-fill molding techniques. Through the use of these highly accurate reflection/diffraction elements, floating images may be formed with relatively high resolution in retro-reflective imaging systems, for example.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karlton Powell, John Lutian
  • Patent number: 9600098
    Abstract: A scroll wheel assembly for computer input device having a housing. The scroll wheel assembly includes a housing and an engagable scroll wheel. The scroll wheel is rotatable with a shaft to preferably cause vertical scrolling of an image on a display. The scroll wheel is laterally tiltable relative to the housing and the shaft. A sensor is preferably positioned within the housing for sensing tilting of the rotatable member. In response to sensed tilting movement of the rotatable member, the image is horizontally scrolled, preferably in the direction of the lateral movement. The computer input device having the rotatable member may take the form of a keyboard, a mouse, a trackball device, or another type of computer input device.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: David D. Bohn
  • Patent number: 9597587
    Abstract: A node device in a distributed virtual environment captures locational signals projected by another node device into a capture area of the node device and reflected from the capture area to a capture device of the node device. The location of the node device relative to the other node device is determined based on the captured locational signals. The determined location can be based on an angular relationship determined between the node device and the other node device based on the captured locational signals. The determined location can also be based on a relative distance determined between the node device and the other node device based on the captured locational signals. Topology of the capture area can also be detected by the node device, and topologies of multiple capture areas can be combined to define one or more surfaces in a virtual environment.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Steven Bathiche
  • Patent number: 9597599
    Abstract: A companion gaming experience is associated with a particular game title, but a user interface for the companion gaming experience is generated by a separate program from the associated game title and is presented on a device separate from the device on which the game user interface itself is presented. When an associated game of the video game title is not running, the companion gaming experience presents guide information and/or statistics data for the game title. However, when an associated game of the game title is running, the companion gaming experience presents gameplay data for the game in near-real-time.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Cesare J. Saretto, Douglas C. Hebenthal, Humberto Castaneda, Kyle A. Pontier, Justin M. Harrison, Andrew Everett Woods
  • Patent number: 9600353
    Abstract: In the field of computing, many scenarios involve the execution of an application within a virtual environment (e.g., web applications executing within a web browser). In order to perform background processing, such applications may invoke worker processes within the virtual environment; however, this configuration couples the life cycle of worker processes to the life cycle of the application and/or virtual environment. Presented herein are techniques for executing worker processes outside of the virtual environment and independently of the life cycle of the application, such that background computation may persist after the application and/or virtual environment are terminated and even after a computing environment restart, and for notifying the application upon the worker process achieving an execution event (e.g., detecting device events even while the application is not executing).
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Blaise Aguera y Arcas, Hen Fitoussi, John Daniell Hebert, Benny Schlesinger, Eran Yariv
  • Patent number: 9600272
    Abstract: Support for dynamic behavior is specified while reducing reliance on JIT compilation and large runtimes; semantic characteristics are selectively attached to types and type members outside source code. A directives document contains human-readable directives in a parsable format for submission to an innovative compiler. The directives specify whether a type T or type member M is required, optional, or prohibited in a runtime environment. Some reference an application, library, assembly, or namespace group, and others reference group components: type, type instantiation, method, method instantiation, field, property, or event. Some directives force a generic instantiation. Some directives indirectly reference a type through a parameter, type parameter, or generic directive. Some directives reference degrees to manage runtime activation of type instances, runtime introspection over types, reflection, and/or runtime or static serialization.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John Lawrence Hamby, David Charles Wrighton, Michal Strehovsky, Morgan Asher Brown, Fadi Hanna, Turgut Isik, Mircea Trofin, Fatma Didem Gokbulut, Robert Yung-Yi Fu
  • Patent number: 9600132
    Abstract: A device identifies a location for a custom RFT command in a message. The custom RTF command is stored in the identified location of the message. The device also receives such messages and detects the custom RTF command in the message and acts upon the detected RTF command.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: David J. Moy
  • Patent number: 9600323
    Abstract: Execution of an application is suspended and the runtime state of the application is collected and persisted. Maintenance operations may then be performed on the computer that the application was executing upon. The runtime state might also be moved to another computer. In order to resume execution of the application, the runtime state of the application is restored. Once the runtime state of the application has been restored, execution of the application may be restarted from the point at which execution was suspended. A proxy layer might also be utilized to translate requests received from the application for resources that are modified after the runtime state of the application is persisted.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Charles Kekeh, Aseem Kohli, Scott Elliot Stearns, Kristofer Hellick Reierson, Cread Wellington Mefford, Angela Mele Anderson
  • Patent number: 9600276
    Abstract: Implementations of the present invention allow software resources to be duplicated efficiently and effectively while offline. In one implementation, a preparation program receives an identification of a software resource, such as a virtual machine installed on a different volume, an offline operating system, or an application program. The preparation program also receives an indication of customized indicia that are to be removed from the software resource. These indicia can include personalized information as well as the level of software updates, security settings, user settings or the like. Upon execution, the preparation program redirects the function calls of the preparation program to the software resource at the different volume (or even the same volume) while the software resource is not running. The preparation program thus can thus creates a template of the software resource in a safe manner without necessarily affecting the volume at which the preparation program runs.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nelson S. Araujo, Steven P. Robertson
  • Patent number: 9600316
    Abstract: The starting up of an application involving multiple virtual machines by overallocating virtual machines. In response to a request to allocate a certain number of virtual machines corresponding to the application, an augmented number of virtual machines is determined to be allocated in response to the request. The augmented number includes both the initially requested number of virtual machines in addition to a surplus number of virtual machines. The virtual machines are then initiated to start up if they are not already started up. Before all of the virtual machines are started up, code is bound to the virtual machines. Thus, because more virtual machines were initiated startup than are required for the application, the code may be bound to some of the virtual machines in the application before all of the virtual machine have started up.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pavel A. Dournov, Denis Samoylov, Anil Ingle
  • Patent number: 9600250
    Abstract: An execution environment in a computer system supports a declarative programming model where user code is written with a query syntax in a native programming language to express inherent parallelism in terms of data flow. The execution environment translates queries in the user code into a runtime agnostic representation and dynamically selects an execution runtime for executing the runtime agnostic representation.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: March 21, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Krishnan Varadarajan, Michael L. Chu
  • Patent number: D781892
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: March 21, 2017
    Assignee: Microsoft Corporation
    Inventors: Sergey Kisselev, Jiwon Choi
  • Patent number: D781893
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: March 21, 2017
    Assignee: Microsoft Corporation
    Inventor: Harold S. Gomez
  • Patent number: D781916
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 21, 2017
    Assignee: Microsoft Corporation
    Inventors: Ramiro Torres, Christina Scott, Raymond Alexander Malkiewicz