Patents Examined by A. Alanko
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Patent number: 11384253Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) an abrasive comprising colloidal silica, (b) a compound of formula (I), (c) a compound of formula (II), (d) hydrogen peroxide, and (e) water, wherein the polishing composition has a pH of about 1 to about 5. The invention also provides a method of chemically-mechanically polishing a substrate, especially a nickel-phosphorous substrate, by contacting the substrate with the inventive chemical-mechanical polishing composition.Type: GrantFiled: December 30, 2019Date of Patent: July 12, 2022Assignee: CMC Materials, Inc.Inventor: Tong Li
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Patent number: 11378882Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.Type: GrantFiled: August 31, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
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Patent number: 11380552Abstract: In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.Type: GrantFiled: April 25, 2020Date of Patent: July 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunchul Yoon, Mincheol Kwak, Joonghee Kim, Jihee Kim, Yeongshin Park, Jungheun Hwang
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Patent number: 11373879Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.Type: GrantFiled: September 12, 2020Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
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Patent number: 11367649Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.Type: GrantFiled: September 29, 2020Date of Patent: June 21, 2022Assignee: GlobalWafers Co., Ltd.Inventors: Hui Wang, Vandan Tanna, Tracy Michelle Ragan, James Raymond Capstick
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Patent number: 11346008Abstract: The invention provides compositions useful for selectively etching ruthenium and/or copper. The compositions comprise certain periodate compounds, alkylammonium or alkylphosphonium hydroxides, carbonate or bicarbonate buffers, and water, wherein the pH of the composition is about 9 to about 12.5. The compositions of the invention are effectively utilized in the method of the invention and have been found to be capable of etching Cu and Ru at similar rates, i.e., >20 ?/min, while minimizing etch rates of dielectrics (<2 ?/min).Type: GrantFiled: November 22, 2019Date of Patent: May 31, 2022Assignee: ENTEGRIS, INC.Inventors: Steven Lippy, Emanuel I. Cooper
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Patent number: 11320592Abstract: The invention relates to a process for fabricating a photonic chip including steps of transferring a die to an actual transfer region of the receiving substrate comprising a central region entirely covered by the die and a peripheral region having a free surface, a first waveguide lying solely in the central region, and a second waveguide lying in the peripheral region; depositing an etch mask on a segment of the die and around the actual transfer region; and dry etching a free segment of the die, the free surface of the peripheral region then being partially etched.Type: GrantFiled: October 23, 2020Date of Patent: May 3, 2022Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Sylvie Menezo, Bertrand Szelag
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Patent number: 11306248Abstract: A silicon etching solution including a component which is a quaternary ammonium hydroxide represented by Formula (A-1), and a component which is a nonionic surfactant, in which an HLB value of the quaternary ammonium hydroxide is in a range of 12 to 15; in Formula (A-1), R1 to R4 each independently represent a monovalent hydrocarbon group, and the total number of carbon atoms contained in R1 to R4 is 10 or greater.Type: GrantFiled: June 18, 2020Date of Patent: April 19, 2022Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Ming-Yen Chung, Masaru Takahama
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Patent number: 11289340Abstract: A dry etching method according to the present invention includes etching silicon nitride by bringing a mixed gas containing hydrogen fluoride and a fluorine-containing carboxylic acid into contact with the silicon nitride in a plasma-less process at a temperature lower than 100° C. Preferably, the amount of the fluorine-containing carboxylic acid contained is 0.01 vol % or more based on the total amount of the hydrogen fluoride and the fluorine-containing carboxylic acid. Examples of the fluorine-containing carboxylic acid are monofluoroacetic acid, difluoroacetic acid, trifluoroacetic acid, difluoropropionic acid, pentafluoropropionic acid, pentafluorobutyric acid and the like. This dry etching method enables etching of the silicon nitride at a high etching rate and shows a high selectivity ratio of the silicon nitride to silicon oxide and polycrystalline silicon while preventing damage to the silicon oxide.Type: GrantFiled: October 24, 2018Date of Patent: March 29, 2022Assignee: Central Glass Company, LimitedInventors: Shoi Suzuki, Akifumi Yao
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Patent number: 11279851Abstract: Provided is a polishing slurry composition including colloidal silica abrasive particles, a metal oxide monomolecular complexing agent, an oxidizer, and a pH adjusting agent, a water-soluble polymer, or both.Type: GrantFiled: May 30, 2019Date of Patent: March 22, 2022Assignee: KCTECH CO., LTD.Inventors: Hyungoo Kong, Jinsook Hwang, Sangmi Lee, Inseol Hwang, Nara Shin
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Patent number: 11268025Abstract: The present disclosure is directed to etching compositions that are useful for, e.g., selectively removing one or both of titanium nitride (TiN) and cobalt (Co) from a semiconductor substrate without substantially forming a cobalt oxide hydroxide layer.Type: GrantFiled: June 2, 2020Date of Patent: March 8, 2022Assignee: Fujifilm Electronic Materials U.S.A., Inc.Inventor: Emil A. Kneer
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Patent number: 11268024Abstract: The present disclosure is directed to etching compositions that are useful for, e.g., selectively removing cobalt (Co) from a semiconductor substrate without substantially forming cobalt oxide by-products.Type: GrantFiled: April 23, 2020Date of Patent: March 8, 2022Assignee: Fujifilm Electronic Materials U.S.A., Inc.Inventor: Emil A. Kneer
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Patent number: 11257673Abstract: A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.Type: GrantFiled: August 19, 2019Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chieh Liao, Cheng-Chi Chuang, Chia-Tien Wu, Tai-I Yang, Hsin-Ping Chen
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Patent number: 11257728Abstract: Embodiments are related to substrates having one or more well structures each exhibiting substantially vertical sidewalls and substantially planar bottoms.Type: GrantFiled: May 31, 2018Date of Patent: February 22, 2022Assignee: Corning IncorporatedInventors: Robert Alan Bellman, Rajesh Vaddi
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Patent number: 11251262Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a cup-shaped lower electrode, a capacitive dielectric layer, an upper electrode, and a support layer. The support layer includes an upper support layer surrounding an upper portion of the cup-shaped lower electrode, a middle support layer surrounding a middle portion of the cup-shaped lower electrode, and a lower support layer surrounding a lower portion of the cup-shaped lower electrode. Surfaces of the upper support layer, the middle support layer, and the lower support layer are covered by the capacitive dielectric layer.Type: GrantFiled: September 25, 2020Date of Patent: February 15, 2022Assignee: Winbond Electronics Corp.Inventors: Yu-Ping Hsiao, Wei-Chao Chou, Ming-Tang Chen, Cheol Soo Park
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Patent number: 11251050Abstract: Systems and methods for processing a workpiece are provided. In one example, a method includes exposing the workpiece to a first gas mixture when the workpiece is at a first temperature to conduct a doped silicate glass etch process. The first gas mixture can include hydrofluoric acid (HF) vapor. The doped silicate glass etch process at least partially removes the doped silicate glass layer at a first etch rate that is greater than a second etch rate associated with removal of the at least one second layer. The method can include heating the workpiece to a second temperature. The second temperature is greater than the first temperature. The method can include exposing the workpiece to a second gas mixture when the workpiece is at a second temperature to remove a residue from the workpiece.Type: GrantFiled: June 18, 2020Date of Patent: February 15, 2022Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.Inventors: Qi Zhang, Xinliang Lu, Hua Chung, Haichun Yang
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Patent number: 11239091Abstract: Embodiments of this disclosure provide methods for etching oxide materials. Some embodiments of this disclosure provide methods which selectively etch oxide materials over other materials. In some embodiments, the methods of this disclosure are performed by atomic layer etching (ALE). In some embodiments, the methods of this disclosure are performed within a processing chamber comprising a nickel chamber material.Type: GrantFiled: June 11, 2020Date of Patent: February 1, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Keenan N. Woods, Zhenjiang Cui, Mark Saly
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Patent number: 11232954Abstract: Substrate processing techniques are described in which an etch protection layer that is formed as part of an etch process forms in a self-limiting nature. Thus, over deposition effects are minimized, particularly in the corners of etched polygonal holes. In one embodiment, the layer being etched contains silicon and the protective layer comprises a silicon oxide (SixOy). The process may include the use of a cyclical series of etch and protective layer formation steps. In the case of a silicon oxide based protective layer, a thin protective layer of silicon oxide may be formed in a limiting and controllable manner due to the nature of the oxygen atom interaction with silicon and newly formed silicon oxide protective layers. In this manner, a polygonal hole may be formed without detrimental over deposition of a protective layer in corners of the hole.Type: GrantFiled: March 16, 2020Date of Patent: January 25, 2022Assignee: Tokyo Electron LimitedInventors: Yu-Hao Tsai, Mingmei Wang
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Patent number: 11227790Abstract: One or more photonic structures are formed within one or more layers over a surface of a substrate, and multiple trenches are formed through the one or more layers housing devices coupled to one or more of the photonic structures. The trenches may include: a first trench that has a bottom surface within the substrate that has a first surface topology characterized by a first surface roughness at a first depth within the substrate relative to the surface of the substrate, and a second trench that has a bottom surface within the substrate that has a second surface topology characterized by a second surface roughness at a second depth within the substrate relative to the surface of the substrate. The first surface roughness may be greater than the second surface roughness, and the second depth may be greater than the first depth.Type: GrantFiled: June 10, 2020Date of Patent: January 18, 2022Assignee: Ciena CorporationInventors: Benoît Filion, Charles Baudot, François Pelletier, Christine Latrasse
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Patent number: 11198796Abstract: A polishing liquid containing abrasive grains, a hydroxy acid, a polyol, a cationic compound, and a liquid medium, in which a zeta potential of the abrasive grains is positive and a weight average molecular weight of the cationic compound is less than 1000.Type: GrantFiled: January 29, 2018Date of Patent: December 14, 2021Assignee: SHOWA DENKO MATERIALS CO., LTD.Inventors: Tomohiro Iwano, Takaaki Matsumoto, Tomoyasu Hasegawa