Abstract: A data processing method and apparatus, a computer device, a readable storage medium, and a computer program product are provided. The method includes: displaying a shot picture in a shooting interface, the shot picture being captured by a shooting component and including a target object; displaying a first virtual rendering area of the target object in the shooting interface in response to a first trigger operation for the target object in the shooting interface; and displaying media data in the first virtual rendering area, the media data being associated with an object classification of the target object.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

Abstract: A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

Abstract: An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

Abstract: Implementations set forth herein relate to effectuating device arbitration in a multi-device environment using data available from a wearable computing device, such as computerized glasses. The computerized glasses can include a camera, which can be used to provide image data for resolving issues related to device arbitration. In some implementations, a direction that a user is directing their computerized glasses, and/or directing their gaze (as detected by the computerized glasses with prior permission from the user), can be used to prioritize a particular device in a multi-device environment. A detected orientation of the computerized glasses can also be used to determine how to simultaneously allocate content between a graphical display of the computerized glasses and another graphical display of another client device. When content is allocated to the computerized glasses, content-specific gestures can be enabled and actionable at the computerized glasses.

Abstract: A method and apparatus for performing a bypass block navigational function to a user interface including generating, by a processor, a webpage including a bypass block navigation attribute associated with a first portion of the webpage, receiving, at a network interface a request for the webpage from the user interface, transmitting, by the network interface, the webpage and a software module including an instruction associated with the bypass block navigation function in response to the request, causing display, at the user interface, the webpage at a starting location, receiving, from the user interface, a keystroke associated with the bypass block navigation function, and causing display, at the user interface, of the first portion of the webpage in response to the instruction associated with the bypass block navigation function.

Abstract: The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.

Abstract: A buffer circuit according to an aspect of the inventive concepts include an operational amplifier configured to amplify an input voltage to generate an output voltage; a slew-rate compensating circuit configured to generate a compensation current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage, and configured to provide the compensation current to the operational amplifier through a boosting transistor; and an offset blocking circuit configured to turn off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is less than a reference voltage level by providing a blocking current to the slew-rate compensating circuit.

Abstract: A display device includes a driving voltage line and a plurality of data lines extending in a first direction, a first driving transistor electrically connected to the driving voltage line, a first switching transistor electrically connected to the first driving transistor and including a first switching semiconductor layer extending in a second direction crossing the first direction and a first switching gate electrode overlapping a channel region of the first switching semiconductor layer, and a first storage capacitor electrically connected to the first driving transistor and the first switching transistor, where the first switching semiconductor layer is electrically connected to a first data line, the first switching semiconductor layer crosses a second data line between the channel region and the first data line, and a crossing region of an edge of the first switching semiconductor layer and an edge of the second data line overlaps a first protection layer.

Abstract: A method comprises forming a gate dielectric cap over a gate structure; forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap laterally between the source/drain contacts; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

Abstract: An electronic device includes an image sensor, a touchscreen display, a transceiver, a processor, and a memory coupled to the processor. The memory stores instructions executable by the processor to receive images of a real world environment via the image sensor; receive, via the touchscreen display, an input for a location of at least one augmented reality anchor point on the received images of the real world environment; receive a selection of at least one virtual object associated with the at least one augmented reality anchor point; output to the touchscreen display the at least one virtual object in proximity to the at least one augmented reality anchor point; generate an augmented reality scene based in part on the at least one augmented reality anchor point and the at least one virtual object; and transmit the augmented reality scene to a receiving device via the transceiver.

Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Abstract: A display device includes a display panel, a power supply a current measurer, a controller, and a sensor. The display panel includes pixels connected between first and second power lines. The power supply applies power voltages to the first and second power lines. The current measurer measures a current applied to the display panel from the power supply through the first and second power lines. The controller outputs a first sensing control signal indicating whether to sense a voltage-current characteristic of the light emitting element of at least one of the pixels based on a measured current. The sensor senses the voltage-current characteristic of the light emitting element in response to the first sensing control signal.

Abstract: A UI for a 3D display is presented in stand by style as a home UI system for a holographic display. The UI provides a live view of a current application and computer game. The behavior of the UI may change according to the distance between an imaged viewer and the display. The UI provides some minimal interaction with the characters in the live view. The UI can be used to control interaction of the holographic display.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: The static random access memory (SRAM) cell of the present disclosure includes a first pull-down device, a second pull-down device, a first pass-gate device, and a second pass-gate device in a first p-well on a substrate; a third pull-down device, a fourth pull-down device, a third pass-gate device, and a fourth pass-gate device in a second p-well on the substrate; a first pull-up device and a second pull-up device in an n-well between the first p-well and the second p-well; and a first landing pad between the second pull-down device and the first pull-up device. The first landing pad is electrically coupled to a gate structure of the second pass-gate device by way of a first gate via.

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.