Patents Examined by A. Sefefr
  • Patent number: 8536042
    Abstract: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John T. Andrews, Hamza Yilmaz, Bruce Marchant, Ihsiu Ho