Abstract: A semiconductor device having resistance to static electricity damage under the CDM is disclosed. The semiconductor device may include a plurality of input/output terminals (102), a first reference electric potential connection (101) electrically connected to the terminals, an input/output protection element (103) electrically connected between the terminals and the first reference electric potential connection (101). A board electric potential generator (104) may provide a potential to a board electric potential connection. A clamp element (105) may be electrically connected between the first reference electric potential and the board electric potential connection.

Abstract: A first plurality of memory cells (32, 33) connected in series lies within a first well (47) that is separated and electrically isolated (42) from a second plurality of memory cells (36 et al.) connected in series lying within a second well (46). In one embodiment, the first and second wells (46, 47) are doped p-type and are contained within an n-well (48) and a substrate (49). Applying a negative voltage to its corresponding bit line and a positive voltage to its corresponding word line programs a predetermined memory cell within the first plurality. A lesser positive voltage than that applied to the predetermined memory cell's word line is applied to all other bit lines and word lines of non-selected memory cells. By utilizing a negative voltage while programming a memory cell, the magnitude of programming voltages is reduced, thereby, removing the need for an elaborate charge pump to generate a much higher programming voltage.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A new ferroelectric memory element is disclosed. The ferroelectric material exhibits little polarization fatigue up to 10.sup.12 switching cycles, long retention and minimal tendency to imprint, producing a nonvolatile, nondestructive readout memory element having low saturation voltage for switching. The memory element can be manufactured using conventional CMOS transistor technology and may include a SrBi.sub.2 Ta.sub.2 O.sub.9 ferroelectric thin-film between metallic electrodes, and an oxide, optionally, conventional SiN.sub.x O.sub.y layer or Si.sub.3 N.sub.4 --SiO.sub.2 bilayer, to protect the substrate from contaminant migration from the ferroelectric layer. Platinum or a metal oxide material (e.g., RuO.sub.2, IrO.sub.2, La.sub.x Sr.sub.1-x CoO.sub.3) may serve as electrodes and provide a lattice matching material for the ferroelectric layer overlying the bottom electrode. Formation of SrBi.sub.2 Ta.sub.2 O.sub.

Abstract: A potential generating circuit includes at least a pair of MOS transistors each of which is diode-connected and series connected between an output node and a given potential node and disposed in same forward direction. Each MOS transistor has its back gate and a gate interconnected. A capacitor is coupled between a connection node of the pair of MOS transistors and an input node to which an alternating signal is inputted.

Abstract: The present invention relates to a flash EEPROM cell, method of manufacturing the same, and method of programming and reading the same and, more particularly, to a flash EEPROM cell constructed in such a way that two floating gates are formed on top of a channel region to implement a memory cell to, and from, which 4-numeration information can be programmed and read out, and an output of 4-numeration information is obtained depending on the programming or erasing of each of the two floating gates.

Abstract: A ferroelectric memory device has a ferroelectric memory capacitor with a hysteresis characteristic adapted to store either a first memory content corresponding to a first polarization condition or a second memory content corresponding to a second polarization condition when there is no applied voltage. A load capacitor is connected in series with the memory capacitor at least at a readout time when the content of the memory capacitor is read out with a readout voltage applied to this series connection. The readout voltage has a polarity different from that of the voltage which will result in the first polarization condition. The memory content of the memory capacitor is determined from the partial voltage generated across the memory capacitor when the readout voltage is applied. A rewrite voltage is applied to the memory capacitor for recovering the polarization condition corresponding to the memory content.