Patents Examined by A. Zavabian
  • Patent number: 5894442
    Abstract: The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: April 13, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichi Okamura
  • Patent number: 5268874
    Abstract: In a reading circuit for a semiconductor memory, connection between a bit line pair 3 and input line of a differential amplifier 4 is controlled using an address transition detection signal LTD. For equalizing the bit line pair 3 in pulse form after transition, the bit line pair 3 is connected to the input terminal of the differential amplifier 4 for a little longer period than the equalizing period, and for clamping the bit line pair 3, the bit line pair 3 and the input terminal of the differential amplifier 4 are disconnected from each other, thus allowing a high-speed, stable reading operation with large-scale capacity.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: December 7, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Yamauchi
  • Patent number: 5220460
    Abstract: A lens mount for positioning a cylindrical lens in x, y, z and .theta..sub.x, .theta..sub.y, .theta..sub.z directional degrees of freedom includes a carrier with a lens-receiving cavity and a spring acting in the cavity adjacent one corner of the lens to apply a biasing torque in the .theta..sub.z direction directly on the lens. The lens is positioned with a planar x-y surface against a corresponding planar x-y surface of the cavity. A plate-like retainer wraps around an opposite curved surface of the lens to hold it in the cavity. Lens adjustments in the magnification x or y axis and .theta..sub.z directions are made against the applied bias by locating screws which pass through the carrier and contact the lens. The .theta..sub.z bias loads opposite lens edges against the .theta..sub.z locating screw and a guide pin, during translational adjustment.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: June 15, 1993
    Assignee: Eastman Kodak Company
    Inventor: Mark Bedzyk