Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.
Type:
Grant
Filed:
February 16, 2016
Date of Patent:
April 2, 2019
Assignee:
International Business Machines Corporation
Inventors:
Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.
Type:
Grant
Filed:
December 15, 2015
Date of Patent:
March 26, 2019
Assignee:
International Business Machines Corporation
Inventors:
Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
Abstract: Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.
Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
Type:
Grant
Filed:
January 13, 2015
Date of Patent:
November 20, 2018
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
Abstract: An approach is provided in which a mapper control unit matches a result instruction tag corresponding to an executed instruction to a history buffer entry's instruction tag. The matched history buffer entry includes multiple history buffer field sets that each include a field set state indicator. The mapper control unit identifies a subset of the history buffer field sets having a valid field set state indicator and stores result data corresponding to the result instruction tag in the identified subset of history buffer field sets. In turn, the mapper control unit restores a subset of a register's fields utilizing content from the subset of history buffer field sets.
Type:
Grant
Filed:
March 25, 2015
Date of Patent:
October 23, 2018
Assignee:
International Business Machines Corporation
Inventors:
Michael J. Genden, Dung Q. Nguyen, Kenneth L. Ward