Abstract: Methods, systems, and computer readable media can be operable to facilitate management of parental control settings at one or more devices based upon a detection of a control device. A central device (115) may be configured with one or more device identifiers of one or more devices that are designated as control devices. In response to a determination by the central device (115) that no control device is connected to the central device (115), the central device (115) may enable one or more parental control settings at the central device (115) and/or one or more client devices (105). When the central device (115) determines that a control device is connected to the central device (115), the central device (115) may disable one or more parental control settings at the central device (115) and/or one or more client devices (105).

Abstract: Acoustic resonator devices and filters are disclosed. An acoustic resonator includes a substrate and a single-crystal piezoelectric plate. A back surface of a supported portion of the piezoelectric plate is attached to a surface of the substrate. A portion of the piezoelectric plate forms a diaphragm that spans a cavity in the substrate. An interdigital transducer (IDT) is formed on a front surface of the piezoelectric plate. The IDT includes first and second busbars, and interleaved fingers extending alternately from the first and second busbars. Overlapping portions of the interleaved fingers are disposed on the diaphragm. At least portions of both the first and second busbars are disposed on the supported portion of the piezoelectric plate.

Abstract: A phase adjusting circuit, a delay locking circuit, and a memory are provided. The phase adjusting circuit includes a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence. The detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference is a preset value.

Abstract: A method for performing, by a first user equipment, wireless communication is proposed. The method may comprise the steps of: transmitting a positioning reference signal (PRS) to a plurality of second user equipments; receiving, from the plurality of second user equipments, location information of the plurality of second user equipments and time of arrival (TOA) values of the plurality of second user equipments; and determining a location of the first user equipment on the basis of the location information of the plurality of second user equipments and the TOA values of the plurality of second user equipments. For example, the TOA values may be determined on the basis of a time when the plurality of second user equipments receive the PRS.

Abstract: A disclosure of the present specification provides a method for a wireless communication device to perform communication based on a plurality of Sims. The method may include the steps of: transmitting a request message to a first network node of a second network, the request message including first information pertaining to the plurality of SIMs; and receiving an acceptance message for the request message from the first network node of the second network.

Abstract: Apparatus and method of powering an outlet in a bed of an all-terrain vehicle. The all-terrain vehicle can include an engine coupled to an electric generator. The method can include activating a generator mode of the engine, generating power by utilizing the electric generator of the all-terrain vehicle coupled to the engine, supplying the power to an inverter, that can convert the power to AC power, and supplying the AC power to the outlet in the bed of the all-terrain vehicle. A controller can discontinue power to at least one accessory when power is supplied to the outlet. The electric generator can be mounted to an air conditioning compressor mount structure of the vehicle.

Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

Abstract: It is provided a method, comprising qualitatively checking if an infrastructure provides all features required to fulfill a request to set up a network slice instance; quantitatively checking if an available capacity of the infrastructure is sufficient to fulfill the request to set up the network slice instance; inhibiting the quantitative checking if, according to the qualitative checking, the infrastructure does not provide all the features required to fulfill the request to set up the network slice instance.

Abstract: A computer-implemented system and method for uploading media to an inspection record via the multimedia messaging service (MMS) are disclosed.

Abstract: Authenticating a mobile user device with a mobile network operator in advance of an MNO authentication request from the mobile user device can be done by a satellite network sending an authentication request to the MNO system, obtaining a set of authentication vectors related to the mobile user device, storing them into a proxy home location register, receiving the MNO authentication request from the mobile user device, generating an authentication request response based on the authentication vectors, sending the authentication request response to the mobile user device, receiving an authentication response including a received signed response, comparing the received signed response with the stored signed response, and if the received signed response and stored signed response match, deem that to be a successful authentication, add an MNO location update message to a request queue and forward the MNO location update message to the MNO system over the channel when available.

Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.

Abstract: Delay locked loop (DLL) circuitry system and a memory device are disclosed. The DLL circuitry system includes a timer unit and a DLL circuit coupled thereto. The timer unit is enabled to generate a DLL enable signal based on the signal instructing the entry into a low power consumption mode and a predefined timer condition. The DLL enable signal enables the DLL circuit to realign an internal clock signal with an external clock signal. In this way, the DLL circuit is avoided from being unable to align the internal clock signal with the external clock signal because the memory device enters the low power mode which causes the variation of the power supply voltage of the DLL circuit. Moreover, a read or write error that may occur when data is to be read or written immediately after exiting the low power consumption mode is also avoided.

Abstract: Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Abstract: An electronic device includes an antenna module configured to perform millimeter wave communication with an external radio frequency device; a radio frequency communication module configured to receive a millimeter wave communication signal transmitted by the external radio frequency device forwarded by the antenna module when the radio frequency communication module is connected with the antenna module; a radio frequency charging module configured to receive a millimeter wave charging signal transmitted by the external radio frequency device forwarded by the antenna module when the radio frequency charging module is electrically connected to the antenna module, and rectify the millimeter wave charging signal into a direct-current signal output; and a processing module electrically connected to the antenna module, the radio frequency communication module, and the radio frequency charging module, respectively to control the electrical connection between the antenna module and the radio frequency communication

Abstract: An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.

Abstract: A voltage controlled oscillator (VCO), including: at least one second upper voltage rail; at least one second lower voltage rail; a ring of N cascaded inverters, wherein the set of N cascaded inverters are coupled between the at least one second upper voltage rail and the at least one second lower voltage rail; at least one first frequency band select circuit coupled between first upper voltage rail and the at least one second upper voltage rail; at least one second frequency band select circuit coupled between the at least one second lower voltage rail and first lower voltage rail; at least one first VCO frequency control circuit coupled between the first upper voltage rail and the at least one second upper voltage rail; and at least one second VCO frequency control circuit coupled between the at least one second lower voltage rail and the first lower voltage rail.

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

Abstract: Disclosed is a filter bank module having a substrate, an antenna port terminal, and a filter bank die. The filter bank die is fixed to the substrate and includes a first acoustic wave (AW) filter having a first antenna terminal coupled to the antenna port terminal and a first filter terminal, wherein the first AW filter is configured to pass a first passband and attenuate frequencies outside the first passband, and a second AW filter having a second filter terminal, and a second antenna terminal coupled to the first antenna terminal to effectively diplex signals that pass through the first AW filter and the second AW filter, wherein the second AW filter is configured to pass a second passband that is spaced from the first passband to minimize interference between first bandpass and the second bandpass while attenuating frequencies outside the second passband.

Abstract: A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.