Abstract: A power transmitter (101) transfers power to a power receiver (105) using a wireless power signal. The power transmitter (101) comprises an inductor (103) driven by a power signal generator (201) to provide the power signal. A calibration controller (211) determines whether a power loss calibration has been performed for the power transmitter (101) and power receiver (105) pairing. The calibration adapts an expected relationship between a received power indication provided by the power receiver (105) and a transmitted power indication for the power transmitter (101). A power limiter (205) restricts the power provided to the inductor to not exceed a threshold unless a power loss calibration has been performed for the pairing. The expected relationship may be used to detect unaccounted for power losses, e.g. due to foreign objects being present. The calibrated expected relationship may provide improved accuracy allowing accurate detection at higher power levels.

Abstract: A non-contact power supply system, in which a first transmission efficiency of supply power in the case of supplying power in a first power supply mode of directly supplying power from a power supply apparatus to a power receiving apparatus and also supplying power to the power receiving apparatus through a relay apparatus, and a second transmission efficiency in the case of supplying the power in a second power supply mode of directly supplying the power from the power supply apparatus to the power receiving apparatus and not supplying the power from the power supply apparatus to the power receiving apparatus through the relay apparatus are compared.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is lower than the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: Systems and methods for process variation power control in three-dimensional integrated circuits (3DICs) are disclosed. In an exemplary aspect, at least one process variation sensor is placed in each tier of a 3DIC. The process variation sensors report information related to a speed characteristic for elements within the respective tier to a decision logic. The decision logic is programmed to weight output from the process variation sensors according to relative importance of logic path segments in the respective tiers. The weighted outputs are combined to generate a power control signal that is sent to a power management unit (PMU). By weighting the importance of the logic path segments, a compromise voltage may be generated by the PMU which is “good enough” for all the elements in the various tiers to provide acceptable performance.

Abstract: A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal.

Abstract: A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise a

Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.

Abstract: Disclosed are a VCOM generation circuit and a liquid crystal display. The VCOM generation circuit has a voltage divider circuit coupled between a power source input end of the VCOM generation circuit and a ground, and a voltage output end; an operational amplifier output circuit, and one input end is coupled to the voltage output end of the voltage divider circuit, and an output end is a VCOM input end of a liquid crystal display, employed for outputting a liquid crystal drive reference voltage VCOM as the liquid crystal display functions to charge a liquid crystal layer; a delay circuit, coupled between the one input end of the operational amplifier output circuit and the ground, and employed for delaying a change rate of the VCOM as the operational amplifier output circuit outputs the VCOM.

Abstract: A state change device may be electrically connected to a switched receptacle, or to both the switched and unswitched receptacles, of an outlet. The state change device may generate a change of state signal when power is applied to, or removed from, the switched receptacle. The state change device may wirelessly communicate the signal. The state change device may include a load control circuit that may be configured to control the amount of power delivered to an electrical load that is electrically connected to the state change device. The state change device may receive commands directed to the load control circuit. The state change device may be deployed in a load control system and may operate as a control entity, such that the state change device may issue commands to one or more load control devices, responsive to the application or removal of power at the switched receptacle.

Abstract: A pulse-transformer-based isolated gate driver circuit uses a small count of high-temperature-qualified components to drive a power semiconductor switch with asymmetrical voltage biases. A differential driver generates a pulse signal from a pulse-width-modulated signal, which is passed to a charge and lock circuit through a transformer. The charge and lock circuit includes an activation path and a deactivation path, which are selectively open to current flow based on positive or negative voltage pulses in the pulse signal, to selectively turn the main semiconductor switch on or off. The charge and lock circuit can lock voltage across the main semiconductor switch to keep the main semiconductor switch in an “on” or and “off” state.

Abstract: A pulse-transformer-based isolated gate driver circuit uses a small count of high-temperature-qualified components to drive a power semiconductor switch with asymmetrical voltage biases. A differential driver generates a pulse signal from a pulse-width-modulated signal, which is passed to a charge and lock circuit through a transformer. The charge and lock circuit includes an activation path and a deactivation path, which are selectively open to current flow based on positive or negative voltage pulses in the pulse signal, to selectively turn the main semiconductor switch on or off. The charge and lock circuit can lock voltage across the main semiconductor switch to keep the main semiconductor switch in an “on” or and “off” state.

Abstract: A phase-locked loop device may include the following elements: a phase frequency detector configured to generate a control signal; a charge pump connected to the phase frequency detector; a loop filter connected to the charge pump and configured to generate a control voltage based on a first current received from the charge pump, wherein the charge pump is configured to generate a second current based on the control signal and a first copy of the control voltage and to provide the second current to the loop filter, the second current being linearly related to the control voltage; a voltage-controlled oscillator connected to the loop filter and configured to generate an output signal based on a second copy of the control voltage, wherein a frequency of the output signal is directly proportional to the control voltage; and a signal processor connected between the voltage-controlled oscillator and the phase frequency detector.

Abstract: A signal processing apparatus includes: a clock generator configured to generate a clock signal having a phase based on a phase of an input signal; a phase modulator configured to shift the phase of the clock signal to generate a phase-shifted clock signal; and a signal synthesizer configured to synthesize the phase-shifted clock signal and the input signal to generate a synthesized signal, wherein the phase modulator is configured to determine a value by which to shift the phase of the clock signal based on an amplitude of the input signal and an amplitude of noise included in the input signal.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.

Abstract: A control circuit is provided for controlling the voltage at the gate terminal of a field effect transistor acting as a switch. The voltage, at for example, the source terminal of the transistor can be provided to a low pass filter and is then voltage translated to provide the gate signal. The filtering can be arranged so as to compensate for the effect of parasitic capacitances within the transistor, thereby linearizing its frequency response. The voltage translation can help to limit voltage differences between the gate and channel of the transistor. This can be significant as relatively fast transistors, as might be used in microwave circuits, may fail with relatively modest voltages at their gates.

Abstract: A driving circuit configured to control at least one switch element is disclosed in the present disclosure. The driving circuit includes a first voltage generating circuit, a second voltage generating circuit and a driving voltage generating circuit. The first voltage generating circuit is configured to generate a first voltage signal. The second voltage generating circuit is configured to generate a second voltage signal. The driving voltage generating circuit is electrically coupled with the first voltage generating circuit and the second voltage generating circuit. The driving voltage generating circuit outputs at least one driving voltage signal according to the first voltage signal and the second voltage signal. The at least one driving voltage signal comprises three levels. At least one level of the levels is lower than zero level.

Abstract: A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

Abstract: An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal.

Abstract: An integrated circuit device implementing a digital phase-locked loop includes a measure period component, an averager component, a generator component, and a compensator component. In the digital phase-locked loop implementation, phase compensation and frequency compensation are separated from one another.

Abstract: A phase-locked loop circuit, which includes a phase frequency detector, a charge pump, a loop low-pass filter, a first voltage-current converter, a second voltage-current converter, a current-controlled oscillator, a frequency divider, a comparator, and a mode controller, where the mode controller is configured to control the switches S1, S2, and S3 included in the loop low-pass filter to connect or disconnect. Using the phase-locked loop circuit, a voltage value of a second control voltage signal VC2 provided for the first voltage-current converter can reach, in a relatively short time, a voltage value of a first control voltage signal VC1 provided for the second voltage-current converter, thereby increasing a speed of establishing the phase-locked loop circuit and implementing a quick response of the phase-locked loop circuit.