Abstract: A flash EEPROM cell structure and a method for forming it. The method of forming the EEPROM cell includes the steps of: forming a plurality of trenches on a substrate, the trenches being filled with an insulating layer; forming bit lines between the trenches and on the substrate; forming an insulating layer on the bit lines; forming a floating gate, with at least one side of it contacting with the bit lines; and simultaneously forming a control gate and an erasing gate. The control gate and the erasing gate cross the bit lines and the floating gate. The erasing gate also extends over the trenches. The floating gate and the erasing gate extend down into the trenches.

Abstract: In a magnetic read/write assembly, a removable fusible-link shorts the magnetoresistive (MR) sensor element to minimize electrical current through the MR sensing element during discharge of static electricity. Other magnetic head assembly elements such as the write coil and MR magnetic shields are also shorted using fusible-links. The fusible-link is removable during the assembly process. The existing terminal pads and wires are used to remove the fusible-link.

Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate -the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.

Abstract: An object of the present invention is to contribute to increase of storage capacity of a memory and to cope with an nonlinear parasitic resistance.The non-volatile memory have a cell applying to multi-bit data by means of a double layered floating gate architecture. The cell comprises: heavily doped layers (drains 3.sub.0 -3.sub.2 and source 2) being formed separated from each other along an arrangement direction L in a semiconductor substrate; a first floating gate 4A being disposed along a direction orthogonal to the direction L between the drains and source above the semiconductor substrate; second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate above the first floating gate and lie along the direction L, close to the drain; program gates 6.sub.1, 6.sub.2 disposed correspondingly to one of the second floating gates; and a control gate 5 extending across the gate 4A above the gate 4A and being disposed along the direction L, close to the source.

Abstract: A rotor rotating integrally with the rotary cylinder is rotatably fitted to a supporting member. A conductive member is arranged on the outer peripheral surface of this rotor. A conductive connecting terminal connectable with the power generating part is arranged at one end of the supporting member and a conductive brush for feeding voltage from the power source generating part to the electronic circuit through the above mentioned conductive member is arranged at the other end of the supporting member. By fitting the supporting member to the chassis without using lead wires and soldering, the power source voltage from the power generating part will be able to be fed to the electronic circuit within the rotary cylinder and the power feeding apparatus will be able to be very easily fitted to the rotary cylinder.

Abstract: In a semiconductor single crystalline substrate provided with a protecting film to prevent autodoping on the reverse surface thereof, for growing a vapor-phase epitaxial layer on the main obverse surface thereof, a width of a chamfer is set for locating an edge-crown occurred in consequence of a vapor-phase epitaxial growth on the chamfer, and a gap of a distance is formed between a periphery of the protecting film and an innermost part of the chamfer on the reverse surface.

Abstract: A magnetic sensor has a three-terminal magnetic device consisting of an emitter, a base, and a collector. A semiconductor layer serving as the collector and a magnetic multilayered film serving as the base form a Schottky junction. The magnetic multilayered film has two magnetic films opposing each other with a nonmagnetic film between them. The emitter constructed of a metal film and the base are connected via a tunnel insulating film. The relationship between the magnetization directions in the magnetic films changes in accordance with an external magnetic field, and this changes the value of a current flowing through the magnetic device. The external magnetic field is sensed on the basis of this change in the current value.

Abstract: A semiconductor device includes a semiconductor body (3) with a semiconductor element (1) with an electrically conducting region (5) on which a capacitor (2) forming a memory element is present with a lower electrode (11), an oxidic ferroelectric dielectric (12), and an upper electrode (13), which lower electrode (11) makes electrical contact with the conducting region (5) and includes a layer with a conductive metal oxide (112) and a layer (111) including platinum. The layer with the conductive metal oxide (112) acts as an oxygen barrier during manufacture. The invention also relates to a method of manufacturing such a semiconductor device. The device is characterized in that the layer including platinum (111) contains more than 15 atom % of a metal capable of forming a conductive metal oxide, and in that the layer (112) with the conductive metal oxide is present between the layer (111) comprising platinum and the ferroelectric dielectric (12).

Abstract: A magnetically controlled logic cell comprising a semiconductor substrate (1) coated with a dielectric film and containing four field-effect transistors; four current supply buses in contact with the transistors and arranged on the surface of the dielectric film (17), two of the buses in question being power supply buses (34, 35), the other two being output buses (36, 37); and a region insulated from the substrate by a layer of concealed dielectric and by side insulation, the region in question containing four contacts configured symmetrically in pairs and connected to said transistors, power supply buses (34, 35) and output buses (36, 37).

Abstract: A cassette for cleaning the capstan and read/write head of a tape drive. The capstan drives a mechanism for cleaning the read/write head, while a cleaning pad simultaneously engages the capstan from the side. As the cleaning cassette is inserted into the tape drive, the engaging extension of the tape drive activates a lever or motor system to move the capstan cleaning pad from a location within the cassette to a cleaning position in contact with the capstan.

Abstract: The present invention provides a floating gate electrode structure in a non-volatile semiconductor memory device. The floating gate electrode comprises a base portion, a contact portion and a head portion. The base portion horizontally extends on a first gate insulation film so as to be positioned over a channel region of a semiconductor substrate. The contact portion upwardly extends from the base portion. The contact portion is provided within a vertical contact hole formed in an inter-layer insulator covering the base portion. The inter-layer insulator encloses bit lines. The bit lines are positioned above the base portion and electrically separated by the inter-layer insulator from both the contact portion and the base portion. The head portion horizontally extends on the inter-layer insulator to be in contact with the contact portion so that the head portion is electrically coupled to the base portion via the contact portion.

Abstract: A head drum assembly for use in a video cassette recorder comprises a rotary shaft, a flange, a plurality of the heads, a rotary drum, and signal transmitting means, wherein the signal transmitting means has a lower stator transformer mounted on a top surface of the stationary drum, the lower stator transformer provided with a plurality of grooves, each of the lower stator grooves being wound with a coil, a stopper ring mounted on the lower stator transformer, a rotor transformer attached on the circumferential protruding portion of the flange and provided with a plurality of grooves on its upper and lower surfaces, each of the upper rotor and the lower rotor grooves being wound with a coil, and an upper stator transformer mounted on the stopper ring and provided with a plurality of grooves, each of the upper stator grooves being wound with a coil, each of the lower stator grooves being aligned with each of the lower rotor grooves and each of the upper stator grooves being aligned with each of the upper rotor

Abstract: In a cassette holder having, on the lower side thereof, a lid unlocking member arranged to unlock the lid of a cassette when the cassette is inserted and a stopper member arranged to stop the cassette by abutting on the front surface of the cassette, the lid unlocking member and the stopper member or at least the lid unlocking member is carried by the support member together with a protruding part which protrudes inward from the inner side of the cassette holder. The support member is arranged on the lower side of the cassette holder to face the inside of the cassette holder.

Abstract: A semiconductor processing method of forming an NMOS field effect transistor includes, a) providing a projecting mesa of semiconductive material from a bulk semiconductor substrate, the mesa defining a semiconductor substrate floor and walls rising upwardly therefrom; b) providing a gate dielectric layer and a gate atop the semiconductive mesa; c) providing a pair of opposing LDD regions within the semiconductive mesa, the respective LDD regions running along one of the mesa walls; and d) providing source and drain diffusion regions within the bulk semiconductor substrate floor which respectively interconnect with the opposing LDD regions of the mesa. NMOS field effect transistors are also disclosed.

Abstract: A pressure differential actuator latching apparatus for a disk drive device is provided. The latching apparatus includes a rotatable body portion, a rigid air vane portion and a latching trap. When a data storage disk of the disk drive is not being rotated, the latching apparatus maintains a transducer actuator assembly of the disk drive in a locked position by engaging the transducer actuator assembly in the latching trap. When the data storage disk is rotated, airflow is generated proximate to the surface of the disk, in the same direction in which the disk is rotated. The transducer actuator assembly, positioned over the surface of the disk, blocks the airflow. The blockage of airflow creates an area of low pressure just downstream of the actuator assembly. The latching apparatus is disposed in a space between the edge of the data storage disk and walls of the housing so that the air vane portion is positioned between the areas of low and ambient pressure.

Abstract: Magnetic sensor comprises a pair of hard magnetic films magnetized inplane in directions substantially perpendicular to the direction of a signal magnetic field and substantially equal to each other, a soft magnetic film formed in the same plane as the pair of hard magnetic films and interposed between the pair of hard magnetic films and held in contact therewith or in proximity thereto, and a signal magnetic field detecting film superposed on the main surface of the soft magnetic film. A magnetic recording.reproducing head using this reproducing head comprises the reproducing head mentioned above, a pair of magnetic pole layers vertically opposed to each other through the medium of a recording gap, and a recording head possessed of a recording track width equal to or smaller than the reproducing track width of the reproducing head. The reproducing track width L.sub.1 is so set as to satisfy the relation, L.sub.2 <L.sub.1 <L.sub.3, wherein L.sub.

Abstract: A Semiconductor-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer. The MOSFET includes a semiconductor surface layer on the buried insulating layer and has a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the second conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region. A semiconductor linkup region of the first conductivity type is provided between the channel region and the drift region and extends substantially through the semiconductor surface layer, and the source region of the device is electrically coupled to the drift region.

Abstract: An optical system driving apparatus includes a holding member holding an optical element and having first and second surfaces facing in opposite directions, and a carriage having first and second surfaces which contact the surfaces of the holding member and slidably clamp the surfaces of the holding member. At least one of a slidable contact surface portion of the first surface of the holding member which corresponds to the first surface of the carriage and a slidable contact surface portion of the first surface of the carriage which corresponds to the first surface of the holding member is formed into an at least partly spherical shape having a center coinciding with an optical center of the optical element, and the other portion guides the holding member to move in a circumferential direction of the spherical slidable contact surface portion.

Abstract: A preferred pnp bipolar phototransistor pixel element in accordance with the present invention has a p-type collector region formed in p-type semiconductor material. An n-type base region is formed in the collector region. A p-type emitter region is formed in the base region. An annular n-type capacitor region is formed in the base region surrounding and spaced-apart from the emitter region. Conductive material is disposed over the capacitor region and separated therefrom by underlying dielectric material to define the pixel element's coupling capacitor.

Abstract: A magnetoresistive head includes a magnetoresistive film and a magnetic domain control layer, formed by a paramagnetic film which is provided in contact with the magnetoresistive film and an antiferromagnetic film which is provided in contact with the paramagnetic film, provided in contact with the magnetoresistive film.